Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3606922	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4343919

1

T1

1045

T2

16

T3

1942

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4310042	1			T1	325		T2	1		T3	2100
values[0x0]	1819398	1			T1	453		T2	15		T3	451
values[0x1]	1821401	1			T1	451		T2	7		T3	427

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2559637	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5391204

1

T1

1081

T2

17

T3

2146

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31624	1			T1	4		T3	8		T4	20
valid_sources[0x01]	39359	1			T1	5		T3	7		T4	40
valid_sources[0x02]	29056	1			T1	2		T3	9		T4	32
valid_sources[0x03]	26773	1			T1	4		T3	13		T4	34
valid_sources[0x04]	32270	1			T1	11		T3	8		T4	37
valid_sources[0x05]	31701	1			T1	8		T3	19		T4	40
valid_sources[0x06]	31321	1			T1	9		T3	15		T4	20
valid_sources[0x07]	29544	1			T1	4		T3	9		T4	39
valid_sources[0x08]	31524	1			T1	6		T3	17		T4	63
valid_sources[0x09]	29425	1			T1	4		T3	13		T4	15
valid_sources[0x0a]	29096	1			T1	8		T3	12		T4	49
valid_sources[0x0b]	34269	1			T1	5		T3	8		T4	66
valid_sources[0x0c]	34530	1			T1	4		T3	9		T4	23
valid_sources[0x0d]	28490	1			T1	1		T3	13		T4	21
valid_sources[0x0e]	31821	1			T1	5		T3	10		T4	51
valid_sources[0x0f]	30842	1			T1	2		T3	10		T4	38
valid_sources[0x10]	28967	1			T1	4		T2	7		T3	11
valid_sources[0x11]	28615	1			T1	5		T3	7		T4	29
valid_sources[0x12]	31284	1			T1	3		T3	10		T4	54
valid_sources[0x13]	28302	1			T1	10		T3	16		T4	30
valid_sources[0x14]	27763	1			T1	3		T3	16		T4	40
valid_sources[0x15]	28758	1			T1	5		T3	13		T4	29
valid_sources[0x16]	28985	1			T1	6		T3	9		T4	14
valid_sources[0x17]	28649	1			T1	6		T3	5		T4	39
valid_sources[0x18]	30772	1			T1	1		T3	14		T4	26
valid_sources[0x19]	32015	1			T1	3		T3	11		T4	63
valid_sources[0x1a]	35517	1			T1	4		T3	10		T4	47
valid_sources[0x1b]	29847	1			T1	5		T3	7		T4	88
valid_sources[0x1c]	29977	1			T1	7		T3	9		T4	37
valid_sources[0x1d]	32397	1			T1	5		T3	8		T4	56
valid_sources[0x1e]	34316	1			T1	9		T3	8		T4	72
valid_sources[0x1f]	30521	1			T1	4		T3	21		T4	24
valid_sources[0x20]	30992	1			T1	4		T3	10		T4	43
valid_sources[0x21]	29480	1			T1	8		T3	11		T4	17
valid_sources[0x22]	29133	1			T1	3		T3	13		T4	44
valid_sources[0x23]	32362	1			T1	2		T3	17		T4	39
valid_sources[0x24]	32614	1			T1	2		T3	8		T4	21
valid_sources[0x25]	30056	1			T1	6		T3	16		T4	52
valid_sources[0x26]	30530	1			T1	6		T3	23		T4	20
valid_sources[0x27]	28160	1			T1	7		T3	14		T4	35
valid_sources[0x28]	27493	1			T1	2		T3	10		T4	21
valid_sources[0x29]	36947	1			T1	6		T3	11		T4	3
valid_sources[0x2a]	29098	1			T1	5		T3	15		T4	20
valid_sources[0x2b]	27900	1			T1	8		T3	12		T4	44
valid_sources[0x2c]	38304	1			T1	2		T3	9		T4	87
valid_sources[0x2d]	29319	1			T1	6		T3	3		T4	32
valid_sources[0x2e]	28886	1			T1	7		T3	16		T4	15
valid_sources[0x2f]	29429	1			T1	4		T2	6		T3	14
valid_sources[0x30]	31694	1			T1	2		T3	13		T4	66
valid_sources[0x31]	30913	1			T1	5		T3	5		T4	48
valid_sources[0x32]	28717	1			T1	1		T3	8		T4	25
valid_sources[0x33]	28297	1			T1	5		T3	14		T4	52
valid_sources[0x34]	32347	1			T1	3		T3	11		T4	41
valid_sources[0x35]	29062	1			T1	5		T3	8		T4	88
valid_sources[0x36]	28357	1			T1	6		T3	11		T4	32
valid_sources[0x37]	32046	1			T1	4		T3	13		T4	49
valid_sources[0x38]	34391	1			T1	5		T3	8		T4	45
valid_sources[0x39]	28188	1			T1	4		T2	1		T3	3
valid_sources[0x3a]	30506	1			T1	5		T3	12		T4	19
valid_sources[0x3b]	29651	1			T1	6		T3	6		T4	46
valid_sources[0x3c]	34963	1			T1	1		T2	1		T3	7
valid_sources[0x3d]	30585	1			T1	6		T3	7		T4	70
valid_sources[0x3e]	30644	1			T1	5		T3	6		T4	30
valid_sources[0x3f]	29463	1			T1	3		T3	18		T4	33
valid_sources[0x40]	32043	1			T1	4		T3	15		T4	37
valid_sources[0x41]	30726	1			T1	2		T3	8		T4	11
valid_sources[0x42]	28494	1			T1	7		T3	10		T4	34
valid_sources[0x43]	28478	1			T1	6		T3	12		T4	37
valid_sources[0x44]	30666	1			T1	2		T3	6		T4	19
valid_sources[0x45]	30593	1			T1	4		T3	14		T4	40
valid_sources[0x46]	28087	1			T1	3		T3	10		T4	22
valid_sources[0x47]	30579	1			T1	6		T3	8		T4	37
valid_sources[0x48]	29063	1			T1	9		T3	21		T4	23
valid_sources[0x49]	36620	1			T1	4		T3	7		T4	16
valid_sources[0x4a]	28438	1			T1	2		T3	7		T4	51
valid_sources[0x4b]	28817	1			T1	2		T3	13		T4	75
valid_sources[0x4c]	33346	1			T1	6		T3	6		T4	29
valid_sources[0x4d]	39914	1			T1	3		T3	12		T4	70
valid_sources[0x4e]	29055	1			T1	4		T3	7		T4	78
valid_sources[0x4f]	26425	1			T1	3		T3	14		T4	29
valid_sources[0x50]	28505	1			T1	3		T3	6		T4	29
valid_sources[0x51]	29410	1			T1	8		T3	10		T4	32
valid_sources[0x52]	29041	1			T1	2		T3	8		T4	21
valid_sources[0x53]	42197	1			T1	7		T2	6		T3	5
valid_sources[0x54]	28505	1			T1	3		T3	6		T4	56
valid_sources[0x55]	38824	1			T1	4		T3	5		T4	30
valid_sources[0x56]	33551	1			T1	7		T3	15		T4	60
valid_sources[0x57]	34272	1			T1	5		T3	6		T4	41
valid_sources[0x58]	27711	1			T1	4		T3	10		T4	66
valid_sources[0x59]	30750	1			T1	2		T3	14		T4	65
valid_sources[0x5a]	28936	1			T1	4		T3	14		T4	35
valid_sources[0x5b]	27701	1			T1	8		T3	9		T4	43
valid_sources[0x5c]	41798	1			T1	4		T3	18		T4	17
valid_sources[0x5d]	30687	1			T1	5		T3	12		T4	104
valid_sources[0x5e]	39222	1			T1	11		T3	14		T4	41
valid_sources[0x5f]	31098	1			T1	4		T3	9		T4	27
valid_sources[0x60]	30662	1			T1	7		T2	2		T3	11
valid_sources[0x61]	32156	1			T1	6		T3	13		T4	42
valid_sources[0x62]	30488	1			T1	6		T3	10		T4	41
valid_sources[0x63]	28090	1			T1	5		T3	16		T4	41
valid_sources[0x64]	27545	1			T1	2		T3	15		T4	25
valid_sources[0x65]	29718	1			T1	7		T3	9		T4	32
valid_sources[0x66]	33352	1			T1	6		T3	16		T4	12
valid_sources[0x67]	28052	1			T1	3		T3	15		T4	56
valid_sources[0x68]	33540	1			T1	5		T3	7		T4	41
valid_sources[0x69]	29682	1			T1	2		T3	6		T4	57
valid_sources[0x6a]	30010	1			T1	5		T3	19		T4	52
valid_sources[0x6b]	30914	1			T1	6		T3	13		T4	37
valid_sources[0x6c]	27451	1			T1	8		T3	9		T4	21
valid_sources[0x6d]	34351	1			T1	5		T3	15		T4	68
valid_sources[0x6e]	32129	1			T1	7		T3	12		T4	35
valid_sources[0x6f]	58482	1			T1	4		T3	9		T4	31
valid_sources[0x70]	30279	1			T1	7		T3	11		T4	56
valid_sources[0x71]	28737	1			T1	5		T3	9		T4	20
valid_sources[0x72]	31430	1			T1	1		T3	13		T4	29
valid_sources[0x73]	31990	1			T1	3		T3	12		T4	38
valid_sources[0x74]	28664	1			T1	6		T3	10		T4	44
valid_sources[0x75]	29866	1			T1	6		T3	9		T4	43
valid_sources[0x76]	29766	1			T1	3		T3	15		T4	15
valid_sources[0x77]	30311	1			T1	8		T3	8		T4	50
valid_sources[0x78]	29686	1			T1	5		T3	6		T4	101
valid_sources[0x79]	28522	1			T1	2		T3	10		T4	18
valid_sources[0x7a]	28921	1			T1	4		T3	13		T4	31
valid_sources[0x7b]	31846	1			T1	6		T3	8		T4	81
valid_sources[0x7c]	30811	1			T1	3		T3	13		T4	20
valid_sources[0x7d]	29044	1			T1	4		T3	22		T4	48
valid_sources[0x7e]	31290	1			T1	2		T3	13		T4	56
valid_sources[0x7f]	31501	1			T1	9		T3	9		T4	34
valid_sources[0x80]	30476	1			T1	2		T3	12		T4	65

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1043641

1

T1

148

T3

1068

T4

1030

values[0x0]

all_enables

biggest_size

1662014

1

T1

451

T2

12

T3

450

values[0x1]

all_enables

biggest_size

1638264

1

T1

446

T2

4

T3

424