Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3629375

1

T1

184

T2

7

T3

1036

full_word

4345320

1

T1

1045

T2

16

T3

1942

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7974335	1			T1	1229		T2	23		T3	2978
auto[TlIntgErrCmd]	121	1			T62	11		T63	5		T92	1
auto[TlIntgErrData]	117	1			T62	8		T63	2		T92	4
auto[TlIntgErrBoth]	122	1			T62	11		T63	3		T92	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4315296

1

T1

325

T2

1

T3

2100

auto[1]

3659399

1

T1

904

T2

22

T3

878

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3271090	1			T1	177		T2	1		T3	1032
auto[TlIntgErrNone]	partial	auto[1]	357961	1			T1	7		T2	6		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	1044036	1			T1	148		T3	1068		T4	1030
auto[TlIntgErrNone]	full_word	auto[1]	3301248	1			T1	897		T2	16		T3	874
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T62	4		T63	2		T93	4
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T62	6		T63	2		T92	1
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T62	1		T108	1		T163	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T63	1		T93	1		T108	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T62	2		T63	2		T92	2
auto[TlIntgErrData]	partial	auto[1]	56	1			T62	5		T92	2		T93	8
auto[TlIntgErrData]	full_word	auto[0]	3	1			T62	1		T164	1		T165	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T93	1		T166	1		T167	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T62	2		T92	3		T93	4
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T62	9		T63	3		T92	2
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T106	1		T166	1		T163	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T108	1		T162	1		T166	1