Unified Coverage Report :: Module :: prim_generic_flop

Module : prim_generic_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_rst_spi_out_sync.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_tpm_rst_out_sync.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_tpm_csb_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_tpm_csb_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spid_csb_sync.u_count_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spid_csb_sync.u_count_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sys_csb_syncd.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sys_csb_syncd.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sys_tpm_csb_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sys_tpm_csb_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_read_pipe_stg1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_read_pipe_stg2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_read_en_pipe_stg1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_read_en_pipe_stg2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_read_intercept_pipe_stg1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_read_intercept_pipe_stg2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spid_status.u_sck2csb_status.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spid_addr_4b.u_spi2sys_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spid_addr_4b.u_spi2sys_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_passthrough.u_read_half_cycle.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_passthrough.u_read_pipe_stg1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_passthrough.u_read_pipe_stg2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_passthrough.u_read_pipe_oe_stg1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_passthrough.u_read_pipe_oe_stg2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spi_tpm.u_wrfifo_busy_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spi_tpm.u_wrfifo_busy_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spi_tpm.u_rdfifo_ready.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spi_tpm.u_rdfifo_ready.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_rst_spi_out_sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_spi_out_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tpm_rst_out_sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_tpm_rst_out_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_csb_sync.u_count_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_csb_sync.u_count_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_csb_syncd.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_csb_syncd.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_tpm_csb_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_tpm_csb_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_read_pipe_stg1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_read_pipe_stg1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_read_pipe_stg2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_read_pipe_stg2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_read_en_pipe_stg1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_read_en_pipe_stg1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_read_en_pipe_stg2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_read_en_pipe_stg2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_read_intercept_pipe_stg1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_read_intercept_pipe_stg1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_read_intercept_pipe_stg2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_read_intercept_pipe_stg2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_status.u_sck2csb_status.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sck2csb_status

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_passthrough.u_read_half_cycle.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_read_half_cycle

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_passthrough.u_read_pipe_stg1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_read_pipe_stg1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_passthrough.u_read_pipe_stg2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_read_pipe_stg2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_passthrough.u_read_pipe_oe_stg1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_read_pipe_oe_stg1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_passthrough.u_read_pipe_oe_stg2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_read_pipe_oe_stg2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_wrfifo_busy_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_wrfifo_busy_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_rdfifo_ready.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_rdfifo_ready.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_flop

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Module : prim_generic_flop

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_rst_spi_out_sync.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_rst_spi_out_sync.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

Line Coverage for Instance : tb.dut.u_tpm_rst_out_sync.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_tpm_rst_out_sync.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

Line Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

Line Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

Line Coverage for Instance : tb.dut.u_spid_csb_sync.u_count_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spid_csb_sync.u_count_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_csb_sync.u_count_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spid_csb_sync.u_count_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sys_csb_syncd.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_sys_csb_syncd.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sys_csb_syncd.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_sys_csb_syncd.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sys_tpm_csb_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_sys_tpm_csb_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sys_tpm_csb_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_sys_tpm_csb_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_read_pipe_stg1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_read_pipe_stg1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

Line Coverage for Instance : tb.dut.u_read_pipe_stg2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_read_pipe_stg2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

Line Coverage for Instance : tb.dut.u_read_en_pipe_stg1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_read_en_pipe_stg1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

Line Coverage for Instance : tb.dut.u_read_en_pipe_stg2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_read_en_pipe_stg2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

Line Coverage for Instance : tb.dut.u_read_intercept_pipe_stg1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_read_intercept_pipe_stg1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

Line Coverage for Instance : tb.dut.u_read_intercept_pipe_stg2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_read_intercept_pipe_stg2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

Line Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_status.u_sck2csb_status.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spid_status.u_sck2csb_status.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_passthrough.u_read_half_cycle.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_passthrough.u_read_half_cycle.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

Line Coverage for Instance : tb.dut.u_passthrough.u_read_pipe_stg1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_passthrough.u_read_pipe_stg1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

Line Coverage for Instance : tb.dut.u_passthrough.u_read_pipe_stg2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_passthrough.u_read_pipe_stg2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

Line Coverage for Instance : tb.dut.u_passthrough.u_read_pipe_oe_stg1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_passthrough.u_read_pipe_oe_stg1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

Line Coverage for Instance : tb.dut.u_passthrough.u_read_pipe_oe_stg2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_passthrough.u_read_pipe_oe_stg2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

Line Coverage for Instance : tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_busy_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_busy_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_busy_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_busy_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo_ready.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo_ready.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

Line Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo_ready.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo_ready.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3