Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444099894	2963096	0	0
DepthKnown_A	444099894	443973185	0	0
RvalidKnown_A	444099894	443973185	0	0
WreadyKnown_A	444099894	443973185	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	2963096	0	0
T1	16973	832	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	306009	5821	0	0
T5	127393	9148	0	0
T6	94079	0	0	0
T7	367088	9980	0	0
T8	672457	3327	0	0
T9	1977	0	0	0
T10	1161	0	0	0
T12	0	1663	0	0
T13	0	832	0	0
T14	0	1663	0	0
T15	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444099894	3522956	0	0
DepthKnown_A	444099894	443973185	0	0
RvalidKnown_A	444099894	443973185	0	0
WreadyKnown_A	444099894	443973185	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3522956	0	0
T1	16973	2702	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	306009	3328	0	0
T5	127393	5824	0	0
T6	94079	0	0	0
T7	367088	6656	0	0
T8	672457	2496	0	0
T9	1977	0	0	0
T10	1161	0	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444099894	199393	0	0
DepthKnown_A	444099894	443973185	0	0
RvalidKnown_A	444099894	443973185	0	0
WreadyKnown_A	444099894	443973185	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	199393	0	0
T4	306009	748	0	0
T5	127393	192	0	0
T6	94079	69	0	0
T7	367088	416	0	0
T8	672457	583	0	0
T9	1977	1	0	0
T10	1161	0	0	0
T11	543621	609	0	0
T12	41700	0	0	0
T14	0	681	0	0
T22	13842	0	0	0
T24	0	16	0	0
T32	0	622	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444099894	486466	0	0
DepthKnown_A	444099894	443973185	0	0
RvalidKnown_A	444099894	443973185	0	0
WreadyKnown_A	444099894	443973185	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	486466	0	0
T4	306009	3169	0	0
T5	127393	192	0	0
T6	94079	69	0	0
T7	367088	416	0	0
T8	672457	583	0	0
T9	1977	1	0	0
T10	1161	0	0	0
T11	543621	609	0	0
T12	41700	0	0	0
T14	0	681	0	0
T22	13842	0	0	0
T24	0	16	0	0
T32	0	2888	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444099894	6186834	0	0
DepthKnown_A	444099894	443973185	0	0
RvalidKnown_A	444099894	443973185	0	0
WreadyKnown_A	444099894	443973185	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	6186834	0	0
T1	16973	397	0	0
T2	2177	23	0	0
T3	31444	2146	0	0
T4	306009	7351	0	0
T5	127393	2095	0	0
T6	94079	1634	0	0
T7	367088	1134	0	0
T8	672457	13104	0	0
T9	1977	53	0	0
T10	1161	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444099894	13478855	0	0
DepthKnown_A	444099894	443973185	0	0
RvalidKnown_A	444099894	443973185	0	0
WreadyKnown_A	444099894	443973185	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	13478855	0	0
T1	16973	1243	0	0
T2	2177	23	0	0
T3	31444	2146	0	0
T4	306009	23527	0	0
T5	127393	2094	0	0
T6	94079	1633	0	0
T7	367088	1133	0	0
T8	672457	13001	0	0
T9	1977	53	0	0
T10	1161	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	443973185	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0