Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T8
1	0	Covered	T4,T6,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Unreachable
1	1	Covered	T4,T6,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T4,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	747243051	593099867	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	747243051	3842467	0	0
GntImpliesValid_A	747243051	3842467	0	0
GrantKnown_A	747243051	593099867	0	0
IdxKnown_A	747243051	593099867	0	0
IndexIsCorrect_A	747243051	3842467	0	0
LockArbDecision_A	747243051	0	0	0
NoReadyValidNoGrant_A	747243051	0	0	0
ReadyAndValidImplyGrant_A	747243051	3842467	0	0
ReqAndReadyImplyGrant_A	747243051	3842467	0	0
ReqImpliesValid_A	747243051	3842467	0	0
ReqStaysHighUntilGranted0_M	747243051	0	0	0
RoundRobin_A	747243051	11	0	956
ValidKnown_A	747243051	593099867	0	0
gen_data_port_assertion.DataFlow_A	747243051	3842467	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747243051	593099867	0	0
T1	35270	34587	0	0
T2	3185	2582	0	0
T3	89076	60181	0	0
T4	900187	599077	0	0
T5	948899	536511	0	0
T6	120351	107146	0	0
T7	1556002	959383	0	0
T8	1009305	836874	0	0
T9	3907	2758	0	0
T10	1161	1063	0	0
T11	173392	83200	0	0
T12	146066	145728	0	0
T13	0	20981	0	0
T14	0	235666	0	0
T15	0	88132	0	0
T22	0	9256	0	0
T23	0	55696	0	0
T24	0	1912	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747243051	3842467	0	0
T1	16973	832	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	900187	7940	0	0
T5	948899	7690	0	0
T6	120351	827	0	0
T7	1556002	17103	0	0
T8	1009305	7064	0	0
T9	3907	36	0	0
T10	1161	0	0	0
T11	173392	4676	0	0
T12	292132	832	0	0
T13	41962	0	0	0
T14	0	3780	0	0
T16	0	1643	0	0
T22	20508	0	0	0
T24	0	85	0	0
T29	0	7372	0	0
T30	0	6561	0	0
T32	0	3656	0	0
T39	0	2361	0	0
T40	0	5731	0	0
T41	0	3329	0	0
T45	0	5257	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747243051	3842467	0	0
T1	16973	832	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	900187	7940	0	0
T5	948899	7690	0	0
T6	120351	827	0	0
T7	1556002	17103	0	0
T8	1009305	7064	0	0
T9	3907	36	0	0
T10	1161	0	0	0
T11	173392	4676	0	0
T12	292132	832	0	0
T13	41962	0	0	0
T14	0	3780	0	0
T16	0	1643	0	0
T22	20508	0	0	0
T24	0	85	0	0
T29	0	7372	0	0
T30	0	6561	0	0
T32	0	3656	0	0
T39	0	2361	0	0
T40	0	5731	0	0
T41	0	3329	0	0
T45	0	5257	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747243051	593099867	0	0
T1	35270	34587	0	0
T2	3185	2582	0	0
T3	89076	60181	0	0
T4	900187	599077	0	0
T5	948899	536511	0	0
T6	120351	107146	0	0
T7	1556002	959383	0	0
T8	1009305	836874	0	0
T9	3907	2758	0	0
T10	1161	1063	0	0
T11	173392	83200	0	0
T12	146066	145728	0	0
T13	0	20981	0	0
T14	0	235666	0	0
T15	0	88132	0	0
T22	0	9256	0	0
T23	0	55696	0	0
T24	0	1912	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747243051	593099867	0	0
T1	35270	34587	0	0
T2	3185	2582	0	0
T3	89076	60181	0	0
T4	900187	599077	0	0
T5	948899	536511	0	0
T6	120351	107146	0	0
T7	1556002	959383	0	0
T8	1009305	836874	0	0
T9	3907	2758	0	0
T10	1161	1063	0	0
T11	173392	83200	0	0
T12	146066	145728	0	0
T13	0	20981	0	0
T14	0	235666	0	0
T15	0	88132	0	0
T22	0	9256	0	0
T23	0	55696	0	0
T24	0	1912	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747243051	3842467	0	0
T1	16973	832	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	900187	7940	0	0
T5	948899	7690	0	0
T6	120351	827	0	0
T7	1556002	17103	0	0
T8	1009305	7064	0	0
T9	3907	36	0	0
T10	1161	0	0	0
T11	173392	4676	0	0
T12	292132	832	0	0
T13	41962	0	0	0
T14	0	3780	0	0
T16	0	1643	0	0
T22	20508	0	0	0
T24	0	85	0	0
T29	0	7372	0	0
T30	0	6561	0	0
T32	0	3656	0	0
T39	0	2361	0	0
T40	0	5731	0	0
T41	0	3329	0	0
T45	0	5257	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747243051	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747243051	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747243051	3842467	0	0
T1	16973	832	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	900187	7940	0	0
T5	948899	7690	0	0
T6	120351	827	0	0
T7	1556002	17103	0	0
T8	1009305	7064	0	0
T9	3907	36	0	0
T10	1161	0	0	0
T11	173392	4676	0	0
T12	292132	832	0	0
T13	41962	0	0	0
T14	0	3780	0	0
T16	0	1643	0	0
T22	20508	0	0	0
T24	0	85	0	0
T29	0	7372	0	0
T30	0	6561	0	0
T32	0	3656	0	0
T39	0	2361	0	0
T40	0	5731	0	0
T41	0	3329	0	0
T45	0	5257	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747243051	3842467	0	0
T1	16973	832	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	900187	7940	0	0
T5	948899	7690	0	0
T6	120351	827	0	0
T7	1556002	17103	0	0
T8	1009305	7064	0	0
T9	3907	36	0	0
T10	1161	0	0	0
T11	173392	4676	0	0
T12	292132	832	0	0
T13	41962	0	0	0
T14	0	3780	0	0
T16	0	1643	0	0
T22	20508	0	0	0
T24	0	85	0	0
T29	0	7372	0	0
T30	0	6561	0	0
T32	0	3656	0	0
T39	0	2361	0	0
T40	0	5731	0	0
T41	0	3329	0	0
T45	0	5257	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747243051	3842467	0	0
T1	16973	832	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	900187	7940	0	0
T5	948899	7690	0	0
T6	120351	827	0	0
T7	1556002	17103	0	0
T8	1009305	7064	0	0
T9	3907	36	0	0
T10	1161	0	0	0
T11	173392	4676	0	0
T12	292132	832	0	0
T13	41962	0	0	0
T14	0	3780	0	0
T16	0	1643	0	0
T22	20508	0	0	0
T24	0	85	0	0
T29	0	7372	0	0
T30	0	6561	0	0
T32	0	3656	0	0
T39	0	2361	0	0
T40	0	5731	0	0
T41	0	3329	0	0
T45	0	5257	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	747243051	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747243051	11	0	956
T16	390197	0	0	1
T29	282184	1	0	1
T30	242301	0	0	1
T31	0	1	0	0
T40	911286	0	0	1
T45	626228	0	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	1443	0	0	1
T54	509473	0	0	1
T55	6674	0	0	1
T56	314941	0	0	1
T57	1718	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747243051	593099867	0	0
T1	35270	34587	0	0
T2	3185	2582	0	0
T3	89076	60181	0	0
T4	900187	599077	0	0
T5	948899	536511	0	0
T6	120351	107146	0	0
T7	1556002	959383	0	0
T8	1009305	836874	0	0
T9	3907	2758	0	0
T10	1161	1063	0	0
T11	173392	83200	0	0
T12	146066	145728	0	0
T13	0	20981	0	0
T14	0	235666	0	0
T15	0	88132	0	0
T22	0	9256	0	0
T23	0	55696	0	0
T24	0	1912	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747243051	3842467	0	0
T1	16973	832	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	900187	7940	0	0
T5	948899	7690	0	0
T6	120351	827	0	0
T7	1556002	17103	0	0
T8	1009305	7064	0	0
T9	3907	36	0	0
T10	1161	0	0	0
T11	173392	4676	0	0
T12	292132	832	0	0
T13	41962	0	0	0
T14	0	3780	0	0
T16	0	1643	0	0
T22	20508	0	0	0
T24	0	85	0	0
T29	0	7372	0	0
T30	0	6561	0	0
T32	0	3656	0	0
T39	0	2361	0	0
T40	0	5731	0	0
T41	0	3329	0	0
T45	0	5257	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T8
1	0	Covered	T4,T6,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Unreachable
1	1	Covered	T4,T6,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T6,T8
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152714513	30770723	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	152714513	680761	0	0
GntImpliesValid_A	152714513	680761	0	0
GrantKnown_A	152714513	30770723	0	0
IdxKnown_A	152714513	30770723	0	0
IndexIsCorrect_A	152714513	680761	0	0
LockArbDecision_A	152714513	0	0	0
NoReadyValidNoGrant_A	152714513	0	0	0
ReadyAndValidImplyGrant_A	152714513	680761	0	0
ReqAndReadyImplyGrant_A	152714513	680761	0	0
ReqImpliesValid_A	152714513	680761	0	0
ReqStaysHighUntilGranted0_M	152714513	0	0	0
RoundRobin_A	152714513	0	0	0
ValidKnown_A	152714513	30770723	0	0
gen_data_port_assertion.DataFlow_A	152714513	680761	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	30770723	0	0
T2	504	504	0	0
T3	28816	0	0	0
T4	297089	90208	0	0
T5	410753	0	0	0
T6	13136	13136	0	0
T7	594457	0	0	0
T8	168424	58464	0	0
T9	965	864	0	0
T11	86696	83200	0	0
T12	146066	0	0	0
T14	0	216384	0	0
T22	0	9256	0	0
T23	0	55696	0	0
T24	0	1912	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	680761	0	0
T4	297089	2555	0	0
T5	410753	0	0	0
T6	13136	519	0	0
T7	594457	0	0	0
T8	168424	2721	0	0
T9	965	20	0	0
T11	86696	3250	0	0
T12	146066	0	0	0
T13	20981	0	0	0
T14	0	3780	0	0
T22	10254	0	0	0
T24	0	85	0	0
T29	0	6332	0	0
T32	0	3656	0	0
T45	0	5257	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	680761	0	0
T4	297089	2555	0	0
T5	410753	0	0	0
T6	13136	519	0	0
T7	594457	0	0	0
T8	168424	2721	0	0
T9	965	20	0	0
T11	86696	3250	0	0
T12	146066	0	0	0
T13	20981	0	0	0
T14	0	3780	0	0
T22	10254	0	0	0
T24	0	85	0	0
T29	0	6332	0	0
T32	0	3656	0	0
T45	0	5257	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	30770723	0	0
T2	504	504	0	0
T3	28816	0	0	0
T4	297089	90208	0	0
T5	410753	0	0	0
T6	13136	13136	0	0
T7	594457	0	0	0
T8	168424	58464	0	0
T9	965	864	0	0
T11	86696	83200	0	0
T12	146066	0	0	0
T14	0	216384	0	0
T22	0	9256	0	0
T23	0	55696	0	0
T24	0	1912	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	30770723	0	0
T2	504	504	0	0
T3	28816	0	0	0
T4	297089	90208	0	0
T5	410753	0	0	0
T6	13136	13136	0	0
T7	594457	0	0	0
T8	168424	58464	0	0
T9	965	864	0	0
T11	86696	83200	0	0
T12	146066	0	0	0
T14	0	216384	0	0
T22	0	9256	0	0
T23	0	55696	0	0
T24	0	1912	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	680761	0	0
T4	297089	2555	0	0
T5	410753	0	0	0
T6	13136	519	0	0
T7	594457	0	0	0
T8	168424	2721	0	0
T9	965	20	0	0
T11	86696	3250	0	0
T12	146066	0	0	0
T13	20981	0	0	0
T14	0	3780	0	0
T22	10254	0	0	0
T24	0	85	0	0
T29	0	6332	0	0
T32	0	3656	0	0
T45	0	5257	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	680761	0	0
T4	297089	2555	0	0
T5	410753	0	0	0
T6	13136	519	0	0
T7	594457	0	0	0
T8	168424	2721	0	0
T9	965	20	0	0
T11	86696	3250	0	0
T12	146066	0	0	0
T13	20981	0	0	0
T14	0	3780	0	0
T22	10254	0	0	0
T24	0	85	0	0
T29	0	6332	0	0
T32	0	3656	0	0
T45	0	5257	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	680761	0	0
T4	297089	2555	0	0
T5	410753	0	0	0
T6	13136	519	0	0
T7	594457	0	0	0
T8	168424	2721	0	0
T9	965	20	0	0
T11	86696	3250	0	0
T12	146066	0	0	0
T13	20981	0	0	0
T14	0	3780	0	0
T22	10254	0	0	0
T24	0	85	0	0
T29	0	6332	0	0
T32	0	3656	0	0
T45	0	5257	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	680761	0	0
T4	297089	2555	0	0
T5	410753	0	0	0
T6	13136	519	0	0
T7	594457	0	0	0
T8	168424	2721	0	0
T9	965	20	0	0
T11	86696	3250	0	0
T12	146066	0	0	0
T13	20981	0	0	0
T14	0	3780	0	0
T22	10254	0	0	0
T24	0	85	0	0
T29	0	6332	0	0
T32	0	3656	0	0
T45	0	5257	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	30770723	0	0
T2	504	504	0	0
T3	28816	0	0	0
T4	297089	90208	0	0
T5	410753	0	0	0
T6	13136	13136	0	0
T7	594457	0	0	0
T8	168424	58464	0	0
T9	965	864	0	0
T11	86696	83200	0	0
T12	146066	0	0	0
T14	0	216384	0	0
T22	0	9256	0	0
T23	0	55696	0	0
T24	0	1912	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	680761	0	0
T4	297089	2555	0	0
T5	410753	0	0	0
T6	13136	519	0	0
T7	594457	0	0	0
T8	168424	2721	0	0
T9	965	20	0	0
T11	86696	3250	0	0
T12	146066	0	0	0
T13	20981	0	0	0
T14	0	3780	0	0
T22	10254	0	0	0
T24	0	85	0	0
T29	0	6332	0	0
T32	0	3656	0	0
T45	0	5257	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T4,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152714513	120600199	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	152714513	795601	0	0
GntImpliesValid_A	152714513	795601	0	0
GrantKnown_A	152714513	120600199	0	0
IdxKnown_A	152714513	120600199	0	0
IndexIsCorrect_A	152714513	795601	0	0
LockArbDecision_A	152714513	0	0	0
NoReadyValidNoGrant_A	152714513	0	0	0
ReadyAndValidImplyGrant_A	152714513	795601	0	0
ReqAndReadyImplyGrant_A	152714513	795601	0	0
ReqImpliesValid_A	152714513	795601	0	0
ReqStaysHighUntilGranted0_M	152714513	0	0	0
RoundRobin_A	152714513	0	0	0
ValidKnown_A	152714513	120600199	0	0
gen_data_port_assertion.DataFlow_A	152714513	795601	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	120600199	0	0
T1	18297	17712	0	0
T2	504	0	0	0
T3	28816	28816	0	0
T4	297089	203025	0	0
T5	410753	409126	0	0
T6	13136	0	0	0
T7	594457	592391	0	0
T8	168424	106011	0	0
T9	965	0	0	0
T11	86696	0	0	0
T12	0	145728	0	0
T13	0	20981	0	0
T14	0	19282	0	0
T15	0	88132	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	795601	0	0
T4	297089	902	0	0
T5	410753	1663	0	0
T6	13136	0	0	0
T7	594457	10010	0	0
T8	168424	497	0	0
T9	965	0	0	0
T11	86696	0	0	0
T12	146066	0	0	0
T13	20981	0	0	0
T16	0	1643	0	0
T22	10254	0	0	0
T29	0	1040	0	0
T30	0	6561	0	0
T39	0	2361	0	0
T40	0	5731	0	0
T41	0	3329	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	795601	0	0
T4	297089	902	0	0
T5	410753	1663	0	0
T6	13136	0	0	0
T7	594457	10010	0	0
T8	168424	497	0	0
T9	965	0	0	0
T11	86696	0	0	0
T12	146066	0	0	0
T13	20981	0	0	0
T16	0	1643	0	0
T22	10254	0	0	0
T29	0	1040	0	0
T30	0	6561	0	0
T39	0	2361	0	0
T40	0	5731	0	0
T41	0	3329	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	120600199	0	0
T1	18297	17712	0	0
T2	504	0	0	0
T3	28816	28816	0	0
T4	297089	203025	0	0
T5	410753	409126	0	0
T6	13136	0	0	0
T7	594457	592391	0	0
T8	168424	106011	0	0
T9	965	0	0	0
T11	86696	0	0	0
T12	0	145728	0	0
T13	0	20981	0	0
T14	0	19282	0	0
T15	0	88132	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	120600199	0	0
T1	18297	17712	0	0
T2	504	0	0	0
T3	28816	28816	0	0
T4	297089	203025	0	0
T5	410753	409126	0	0
T6	13136	0	0	0
T7	594457	592391	0	0
T8	168424	106011	0	0
T9	965	0	0	0
T11	86696	0	0	0
T12	0	145728	0	0
T13	0	20981	0	0
T14	0	19282	0	0
T15	0	88132	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	795601	0	0
T4	297089	902	0	0
T5	410753	1663	0	0
T6	13136	0	0	0
T7	594457	10010	0	0
T8	168424	497	0	0
T9	965	0	0	0
T11	86696	0	0	0
T12	146066	0	0	0
T13	20981	0	0	0
T16	0	1643	0	0
T22	10254	0	0	0
T29	0	1040	0	0
T30	0	6561	0	0
T39	0	2361	0	0
T40	0	5731	0	0
T41	0	3329	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	795601	0	0
T4	297089	902	0	0
T5	410753	1663	0	0
T6	13136	0	0	0
T7	594457	10010	0	0
T8	168424	497	0	0
T9	965	0	0	0
T11	86696	0	0	0
T12	146066	0	0	0
T13	20981	0	0	0
T16	0	1643	0	0
T22	10254	0	0	0
T29	0	1040	0	0
T30	0	6561	0	0
T39	0	2361	0	0
T40	0	5731	0	0
T41	0	3329	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	795601	0	0
T4	297089	902	0	0
T5	410753	1663	0	0
T6	13136	0	0	0
T7	594457	10010	0	0
T8	168424	497	0	0
T9	965	0	0	0
T11	86696	0	0	0
T12	146066	0	0	0
T13	20981	0	0	0
T16	0	1643	0	0
T22	10254	0	0	0
T29	0	1040	0	0
T30	0	6561	0	0
T39	0	2361	0	0
T40	0	5731	0	0
T41	0	3329	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	795601	0	0
T4	297089	902	0	0
T5	410753	1663	0	0
T6	13136	0	0	0
T7	594457	10010	0	0
T8	168424	497	0	0
T9	965	0	0	0
T11	86696	0	0	0
T12	146066	0	0	0
T13	20981	0	0	0
T16	0	1643	0	0
T22	10254	0	0	0
T29	0	1040	0	0
T30	0	6561	0	0
T39	0	2361	0	0
T40	0	5731	0	0
T41	0	3329	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	120600199	0	0
T1	18297	17712	0	0
T2	504	0	0	0
T3	28816	28816	0	0
T4	297089	203025	0	0
T5	410753	409126	0	0
T6	13136	0	0	0
T7	594457	592391	0	0
T8	168424	106011	0	0
T9	965	0	0	0
T11	86696	0	0	0
T12	0	145728	0	0
T13	0	20981	0	0
T14	0	19282	0	0
T15	0	88132	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152714513	795601	0	0
T4	297089	902	0	0
T5	410753	1663	0	0
T6	13136	0	0	0
T7	594457	10010	0	0
T8	168424	497	0	0
T9	965	0	0	0
T11	86696	0	0	0
T12	146066	0	0	0
T13	20981	0	0	0
T16	0	1643	0	0
T22	10254	0	0	0
T29	0	1040	0	0
T30	0	6561	0	0
T39	0	2361	0	0
T40	0	5731	0	0
T41	0	3329	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441814025	441728945	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	441814025	2366105	0	0
GntImpliesValid_A	441814025	2366105	0	0
GrantKnown_A	441814025	441728945	0	0
IdxKnown_A	441814025	441728945	0	0
IndexIsCorrect_A	441814025	2366105	0	0
LockArbDecision_A	441814025	0	0	0
NoReadyValidNoGrant_A	441814025	0	0	0
ReadyAndValidImplyGrant_A	441814025	2366105	0	0
ReqAndReadyImplyGrant_A	441814025	2366105	0	0
ReqImpliesValid_A	441814025	2366105	0	0
ReqStaysHighUntilGranted0_M	441814025	0	0	0
RoundRobin_A	441814025	11	0	956
ValidKnown_A	441814025	441728945	0	0
gen_data_port_assertion.DataFlow_A	441814025	2366105	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441814025	441728945	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441814025	2366105	0	0
T1	16973	832	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	306009	4483	0	0
T5	127393	6027	0	0
T6	94079	308	0	0
T7	367088	7093	0	0
T8	672457	3846	0	0
T9	1977	16	0	0
T10	1161	0	0	0
T11	0	1426	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441814025	2366105	0	0
T1	16973	832	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	306009	4483	0	0
T5	127393	6027	0	0
T6	94079	308	0	0
T7	367088	7093	0	0
T8	672457	3846	0	0
T9	1977	16	0	0
T10	1161	0	0	0
T11	0	1426	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441814025	441728945	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441814025	441728945	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441814025	2366105	0	0
T1	16973	832	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	306009	4483	0	0
T5	127393	6027	0	0
T6	94079	308	0	0
T7	367088	7093	0	0
T8	672457	3846	0	0
T9	1977	16	0	0
T10	1161	0	0	0
T11	0	1426	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441814025	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441814025	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441814025	2366105	0	0
T1	16973	832	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	306009	4483	0	0
T5	127393	6027	0	0
T6	94079	308	0	0
T7	367088	7093	0	0
T8	672457	3846	0	0
T9	1977	16	0	0
T10	1161	0	0	0
T11	0	1426	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441814025	2366105	0	0
T1	16973	832	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	306009	4483	0	0
T5	127393	6027	0	0
T6	94079	308	0	0
T7	367088	7093	0	0
T8	672457	3846	0	0
T9	1977	16	0	0
T10	1161	0	0	0
T11	0	1426	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441814025	2366105	0	0
T1	16973	832	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	306009	4483	0	0
T5	127393	6027	0	0
T6	94079	308	0	0
T7	367088	7093	0	0
T8	672457	3846	0	0
T9	1977	16	0	0
T10	1161	0	0	0
T11	0	1426	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441814025	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441814025	11	0	956
T16	390197	0	0	1
T29	282184	1	0	1
T30	242301	0	0	1
T31	0	1	0	0
T40	911286	0	0	1
T45	626228	0	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	1443	0	0	1
T54	509473	0	0	1
T55	6674	0	0	1
T56	314941	0	0	1
T57	1718	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441814025	441728945	0	0
T1	16973	16875	0	0
T2	2177	2078	0	0
T3	31444	31365	0	0
T4	306009	305844	0	0
T5	127393	127385	0	0
T6	94079	94010	0	0
T7	367088	366992	0	0
T8	672457	672399	0	0
T9	1977	1894	0	0
T10	1161	1063	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441814025	2366105	0	0
T1	16973	832	0	0
T2	2177	0	0	0
T3	31444	832	0	0
T4	306009	4483	0	0
T5	127393	6027	0	0
T6	94079	308	0	0
T7	367088	7093	0	0
T8	672457	3846	0	0
T9	1977	16	0	0
T10	1161	0	0	0
T11	0	1426	0	0
T12	0	832	0	0