Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	444099894	2916	0	0
addr_swap_data_rd_A	444099894	1253	0	0
addr_swap_mask_rd_A	444099894	1139	0	0
cfg_rd_A	444099894	1464	0	0
cmd_filter_0_rd_A	444099894	6929	0	0
cmd_filter_1_rd_A	444099894	7043	0	0
cmd_filter_2_rd_A	444099894	7086	0	0
cmd_filter_3_rd_A	444099894	7712	0	0
cmd_filter_4_rd_A	444099894	6628	0	0
cmd_filter_5_rd_A	444099894	6555	0	0
cmd_filter_6_rd_A	444099894	7634	0	0
cmd_filter_7_rd_A	444099894	8217	0	0
cmd_info_0_rd_A	444099894	3484	0	0
cmd_info_10_rd_A	444099894	3360	0	0
cmd_info_11_rd_A	444099894	3578	0	0
cmd_info_12_rd_A	444099894	3491	0	0
cmd_info_13_rd_A	444099894	3493	0	0
cmd_info_14_rd_A	444099894	3463	0	0
cmd_info_15_rd_A	444099894	3477	0	0
cmd_info_16_rd_A	444099894	3523	0	0
cmd_info_17_rd_A	444099894	3694	0	0
cmd_info_18_rd_A	444099894	3298	0	0
cmd_info_19_rd_A	444099894	3496	0	0
cmd_info_1_rd_A	444099894	3456	0	0
cmd_info_20_rd_A	444099894	3590	0	0
cmd_info_21_rd_A	444099894	3446	0	0
cmd_info_22_rd_A	444099894	3331	0	0
cmd_info_23_rd_A	444099894	3529	0	0
cmd_info_2_rd_A	444099894	3309	0	0
cmd_info_3_rd_A	444099894	3440	0	0
cmd_info_4_rd_A	444099894	3108	0	0
cmd_info_5_rd_A	444099894	3608	0	0
cmd_info_6_rd_A	444099894	3734	0	0
cmd_info_7_rd_A	444099894	3528	0	0
cmd_info_8_rd_A	444099894	3747	0	0
cmd_info_9_rd_A	444099894	3257	0	0
cmd_info_en4b_rd_A	444099894	1587	0	0
cmd_info_ex4b_rd_A	444099894	1373	0	0
cmd_info_wrdi_rd_A	444099894	1336	0	0
cmd_info_wren_rd_A	444099894	1461	0	0
intercept_en_rd_A	444099894	1873	0	0
intr_enable_rd_A	444099894	3379	0	0
jedec_cc_rd_A	444099894	1374	0	0
jedec_id_rd_A	444099894	1283	0	0
mailbox_addr_rd_A	444099894	1226	0	0
payload_swap_data_rd_A	444099894	1078	0	0
payload_swap_mask_rd_A	444099894	1143	0	0
read_threshold_rd_A	444099894	1057	0	0
tpm_access_0_rd_A	444099894	1686	0	0
tpm_access_1_rd_A	444099894	1120	0	0
tpm_cfg_rd_A	444099894	2071	0	0
tpm_did_vid_rd_A	444099894	1312	0	0
tpm_int_enable_rd_A	444099894	1246	0	0
tpm_int_status_rd_A	444099894	1190	0	0
tpm_int_vector_rd_A	444099894	1156	0	0
tpm_intf_capability_rd_A	444099894	1231	0	0
tpm_rid_rd_A	444099894	1153	0	0
tpm_sts_rd_A	444099894	1296	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	2916	0	0
T61	7988	77	0	0
T62	90148	3	0	0
T63	26849	2	0	0
T90	15183	4	0	0
T91	5087	16	0	0
T92	27893	1	0	0
T93	97886	4	0	0
T94	4829	110	0	0
T95	4744	3	0	0
T104	16253	8	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1253	0	0
T62	90148	63	0	0
T79	4720	6	0	0
T90	15183	24	0	0
T93	97886	123	0	0
T104	16253	23	0	0
T107	15873	17	0	0
T111	7885	7	0	0
T146	42210	246	0	0
T147	7713	33	0	0
T148	7776	10	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1139	0	0
T62	90148	62	0	0
T79	4720	16	0	0
T90	15183	31	0	0
T93	97886	91	0	0
T95	4744	11	0	0
T104	16253	12	0	0
T111	7885	9	0	0
T146	42210	254	0	0
T147	7713	30	0	0
T148	7776	4	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1464	0	0
T62	90148	120	0	0
T79	4720	7	0	0
T90	15183	40	0	0
T93	97886	188	0	0
T95	4744	1	0	0
T104	16253	38	0	0
T111	7885	17	0	0
T146	42210	235	0	0
T147	7713	13	0	0
T148	7776	12	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	6929	0	0
T62	90148	1052	0	0
T79	4720	18	0	0
T90	15183	129	0	0
T93	97886	1933	0	0
T95	4744	18	0	0
T104	16253	270	0	0
T111	7885	16	0	0
T146	42210	251	0	0
T147	7713	22	0	0
T148	7776	186	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	7043	0	0
T62	90148	1064	0	0
T79	4720	18	0	0
T90	15183	267	0	0
T93	97886	1839	0	0
T95	4744	76	0	0
T104	16253	236	0	0
T111	7885	130	0	0
T146	42210	263	0	0
T147	7713	8	0	0
T148	7776	169	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	7086	0	0
T62	90148	795	0	0
T79	4720	15	0	0
T90	15183	356	0	0
T93	97886	1986	0	0
T95	4744	4	0	0
T104	16253	278	0	0
T111	7885	118	0	0
T146	42210	256	0	0
T147	7713	16	0	0
T148	7776	109	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	7712	0	0
T62	90148	934	0	0
T79	4720	12	0	0
T90	15183	116	0	0
T93	97886	1895	0	0
T95	4744	68	0	0
T104	16253	258	0	0
T111	7885	3	0	0
T146	42210	260	0	0
T147	7713	41	0	0
T148	7776	148	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	6628	0	0
T62	90148	891	0	0
T79	4720	3	0	0
T90	15183	252	0	0
T93	97886	1441	0	0
T95	4744	86	0	0
T104	16253	281	0	0
T111	7885	5	0	0
T146	42210	250	0	0
T147	7713	37	0	0
T148	7776	130	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	6555	0	0
T62	90148	1131	0	0
T79	4720	13	0	0
T90	15183	287	0	0
T93	97886	1226	0	0
T95	4744	53	0	0
T104	16253	119	0	0
T111	7885	213	0	0
T146	42210	273	0	0
T147	7713	15	0	0
T148	7776	67	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	7634	0	0
T62	90148	1293	0	0
T79	4720	11	0	0
T90	15183	142	0	0
T93	97886	1932	0	0
T95	4744	2	0	0
T104	16253	341	0	0
T111	7885	267	0	0
T146	42210	246	0	0
T147	7713	29	0	0
T148	7776	132	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	8217	0	0
T62	90148	1006	0	0
T79	4720	15	0	0
T90	15183	117	0	0
T93	97886	2617	0	0
T95	4744	6	0	0
T104	16253	254	0	0
T111	7885	210	0	0
T146	42210	274	0	0
T147	7713	11	0	0
T148	7776	62	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3484	0	0
T62	90148	483	0	0
T79	4720	16	0	0
T90	15183	153	0	0
T93	97886	829	0	0
T95	4744	16	0	0
T104	16253	84	0	0
T111	7885	7	0	0
T146	42210	287	0	0
T147	7713	22	0	0
T148	7776	2	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3360	0	0
T62	90148	409	0	0
T79	4720	10	0	0
T90	15183	109	0	0
T93	97886	834	0	0
T95	4744	1	0	0
T104	16253	89	0	0
T111	7885	104	0	0
T146	42210	234	0	0
T147	7713	53	0	0
T148	7776	2	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3578	0	0
T62	90148	578	0	0
T79	4720	4	0	0
T90	15183	116	0	0
T93	97886	890	0	0
T95	4744	7	0	0
T104	16253	99	0	0
T111	7885	55	0	0
T146	42210	268	0	0
T147	7713	36	0	0
T148	7776	23	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3491	0	0
T62	90148	467	0	0
T79	4720	4	0	0
T90	15183	88	0	0
T93	97886	655	0	0
T95	4744	30	0	0
T104	16253	144	0	0
T111	7885	87	0	0
T146	42210	269	0	0
T147	7713	45	0	0
T148	7776	25	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3493	0	0
T62	90148	519	0	0
T79	4720	7	0	0
T90	15183	108	0	0
T93	97886	627	0	0
T95	4744	2	0	0
T104	16253	77	0	0
T111	7885	65	0	0
T146	42210	231	0	0
T147	7713	37	0	0
T148	7776	43	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3463	0	0
T62	90148	316	0	0
T79	4720	9	0	0
T90	15183	86	0	0
T93	97886	781	0	0
T104	16253	19	0	0
T107	15873	65	0	0
T111	7885	49	0	0
T146	42210	282	0	0
T147	7713	44	0	0
T148	7776	52	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3477	0	0
T62	90148	464	0	0
T79	4720	14	0	0
T90	15183	61	0	0
T93	97886	671	0	0
T95	4744	9	0	0
T104	16253	73	0	0
T111	7885	101	0	0
T146	42210	223	0	0
T147	7713	39	0	0
T148	7776	3	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3523	0	0
T62	90148	515	0	0
T79	4720	12	0	0
T90	15183	82	0	0
T93	97886	573	0	0
T95	4744	7	0	0
T104	16253	101	0	0
T111	7885	44	0	0
T146	42210	244	0	0
T147	7713	11	0	0
T148	7776	41	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3694	0	0
T62	90148	405	0	0
T79	4720	15	0	0
T90	15183	115	0	0
T93	97886	840	0	0
T95	4744	20	0	0
T104	16253	64	0	0
T111	7885	70	0	0
T146	42210	293	0	0
T147	7713	28	0	0
T148	7776	2	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3298	0	0
T62	90148	417	0	0
T79	4720	10	0	0
T90	15183	19	0	0
T93	97886	694	0	0
T95	4744	7	0	0
T104	16253	98	0	0
T111	7885	8	0	0
T146	42210	272	0	0
T147	7713	1	0	0
T148	7776	29	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3496	0	0
T62	90148	467	0	0
T79	4720	10	0	0
T90	15183	110	0	0
T93	97886	705	0	0
T95	4744	5	0	0
T104	16253	77	0	0
T107	15873	142	0	0
T111	7885	54	0	0
T146	42210	263	0	0
T148	7776	6	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3456	0	0
T62	90148	386	0	0
T79	4720	3	0	0
T90	15183	129	0	0
T93	97886	725	0	0
T95	4744	27	0	0
T104	16253	124	0	0
T111	7885	56	0	0
T146	42210	285	0	0
T147	7713	10	0	0
T148	7776	7	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3590	0	0
T62	90148	459	0	0
T79	4720	13	0	0
T90	15183	26	0	0
T93	97886	876	0	0
T95	4744	37	0	0
T104	16253	121	0	0
T111	7885	47	0	0
T146	42210	238	0	0
T147	7713	37	0	0
T148	7776	22	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3446	0	0
T62	90148	413	0	0
T79	4720	15	0	0
T90	15183	185	0	0
T93	97886	956	0	0
T95	4744	21	0	0
T104	16253	113	0	0
T111	7885	70	0	0
T146	42210	265	0	0
T147	7713	14	0	0
T148	7776	24	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3331	0	0
T62	90148	422	0	0
T79	4720	3	0	0
T90	15183	71	0	0
T93	97886	918	0	0
T104	16253	51	0	0
T107	15873	67	0	0
T111	7885	42	0	0
T116	7723	42	0	0
T146	42210	250	0	0
T147	7713	30	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3529	0	0
T62	90148	392	0	0
T79	4720	8	0	0
T90	15183	120	0	0
T93	97886	693	0	0
T95	4744	49	0	0
T104	16253	67	0	0
T111	7885	65	0	0
T146	42210	254	0	0
T147	7713	33	0	0
T148	7776	29	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3309	0	0
T62	90148	262	0	0
T79	4720	8	0	0
T90	15183	31	0	0
T93	97886	591	0	0
T95	4744	25	0	0
T104	16253	70	0	0
T111	7885	100	0	0
T146	42210	280	0	0
T147	7713	46	0	0
T148	7776	29	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3440	0	0
T62	90148	602	0	0
T79	4720	3	0	0
T90	15183	142	0	0
T93	97886	675	0	0
T95	4744	2	0	0
T104	16253	57	0	0
T111	7885	14	0	0
T146	42210	266	0	0
T147	7713	24	0	0
T148	7776	10	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3108	0	0
T62	90148	404	0	0
T79	4720	10	0	0
T90	15183	63	0	0
T93	97886	736	0	0
T95	4744	1	0	0
T104	16253	20	0	0
T111	7885	45	0	0
T146	42210	299	0	0
T147	7713	8	0	0
T148	7776	37	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3608	0	0
T62	90148	433	0	0
T79	4720	4	0	0
T90	15183	16	0	0
T93	97886	1006	0	0
T95	4744	24	0	0
T104	16253	27	0	0
T111	7885	18	0	0
T146	42210	223	0	0
T147	7713	29	0	0
T148	7776	35	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3734	0	0
T62	90148	529	0	0
T79	4720	10	0	0
T90	15183	82	0	0
T93	97886	791	0	0
T95	4744	6	0	0
T104	16253	205	0	0
T111	7885	50	0	0
T146	42210	277	0	0
T147	7713	29	0	0
T148	7776	51	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3528	0	0
T62	90148	557	0	0
T79	4720	10	0	0
T90	15183	85	0	0
T93	97886	826	0	0
T95	4744	2	0	0
T104	16253	110	0	0
T111	7885	50	0	0
T146	42210	257	0	0
T147	7713	17	0	0
T148	7776	25	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3747	0	0
T62	90148	515	0	0
T79	4720	10	0	0
T90	15183	122	0	0
T93	97886	928	0	0
T95	4744	26	0	0
T104	16253	182	0	0
T107	15873	182	0	0
T111	7885	61	0	0
T146	42210	279	0	0
T148	7776	2	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3257	0	0
T62	90148	528	0	0
T79	4720	11	0	0
T90	15183	14	0	0
T93	97886	857	0	0
T95	4744	2	0	0
T104	16253	24	0	0
T111	7885	49	0	0
T146	42210	284	0	0
T147	7713	33	0	0
T148	7776	34	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1587	0	0
T62	90148	79	0	0
T79	4720	14	0	0
T90	15183	52	0	0
T93	97886	183	0	0
T95	4744	2	0	0
T104	16253	39	0	0
T111	7885	10	0	0
T146	42210	288	0	0
T147	7713	59	0	0
T148	7776	9	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1373	0	0
T62	90148	90	0	0
T79	4720	9	0	0
T90	15183	24	0	0
T93	97886	183	0	0
T95	4744	1	0	0
T104	16253	27	0	0
T111	7885	5	0	0
T146	42210	292	0	0
T147	7713	19	0	0
T148	7776	16	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1336	0	0
T62	90148	120	0	0
T79	4720	14	0	0
T90	15183	34	0	0
T93	97886	199	0	0
T95	4744	5	0	0
T104	16253	55	0	0
T107	15873	34	0	0
T111	7885	21	0	0
T146	42210	252	0	0
T148	7776	3	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1461	0	0
T62	90148	89	0	0
T79	4720	5	0	0
T90	15183	36	0	0
T93	97886	134	0	0
T95	4744	7	0	0
T104	16253	29	0	0
T111	7885	20	0	0
T146	42210	238	0	0
T147	7713	12	0	0
T148	7776	2	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1873	0	0
T62	90148	189	0	0
T79	4720	14	0	0
T90	15183	46	0	0
T93	97886	235	0	0
T104	16253	50	0	0
T107	15873	45	0	0
T111	7885	23	0	0
T146	42210	303	0	0
T147	7713	6	0	0
T148	7776	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	3379	0	0
T4	306009	35	0	0
T5	127393	0	0	0
T6	94079	0	0	0
T7	367088	0	0	0
T8	672457	0	0	0
T9	1977	0	0	0
T10	1161	0	0	0
T11	543621	0	0	0
T12	41700	0	0	0
T19	0	27	0	0
T20	0	5	0	0
T22	13842	0	0	0
T130	0	6	0	0
T149	0	68	0	0
T150	0	55	0	0
T151	0	43	0	0
T152	0	37	0	0
T153	0	24	0	0
T154	0	18	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1374	0	0
T62	90148	95	0	0
T79	4720	12	0	0
T90	15183	27	0	0
T93	97886	220	0	0
T95	4744	1	0	0
T104	16253	39	0	0
T111	7885	12	0	0
T146	42210	222	0	0
T147	7713	42	0	0
T148	7776	5	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1283	0	0
T62	90148	63	0	0
T79	4720	4	0	0
T90	15183	30	0	0
T93	97886	165	0	0
T104	16253	26	0	0
T107	15873	25	0	0
T111	7885	12	0	0
T116	7723	9	0	0
T146	42210	262	0	0
T147	7713	27	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1226	0	0
T62	90148	68	0	0
T79	4720	8	0	0
T90	15183	16	0	0
T93	97886	111	0	0
T95	4744	1	0	0
T104	16253	21	0	0
T111	7885	7	0	0
T146	42210	312	0	0
T147	7713	22	0	0
T148	7776	6	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1078	0	0
T62	90148	21	0	0
T79	4720	21	0	0
T90	15183	29	0	0
T93	97886	100	0	0
T95	4744	1	0	0
T104	16253	15	0	0
T111	7885	3	0	0
T146	42210	282	0	0
T147	7713	20	0	0
T148	7776	7	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1143	0	0
T62	90148	36	0	0
T79	4720	19	0	0
T90	15183	20	0	0
T93	97886	101	0	0
T95	4744	8	0	0
T104	16253	18	0	0
T111	7885	5	0	0
T146	42210	274	0	0
T147	7713	30	0	0
T148	7776	2	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1057	0	0
T62	90148	62	0	0
T79	4720	12	0	0
T90	15183	24	0	0
T93	97886	80	0	0
T95	4744	6	0	0
T104	16253	20	0	0
T111	7885	10	0	0
T146	42210	238	0	0
T147	7713	5	0	0
T148	7776	5	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1686	0	0
T62	90148	199	0	0
T79	4720	16	0	0
T90	15183	15	0	0
T93	97886	290	0	0
T104	16253	19	0	0
T107	15873	30	0	0
T111	7885	1	0	0
T146	42210	195	0	0
T147	7713	4	0	0
T148	7776	9	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1120	0	0
T62	90148	69	0	0
T79	4720	11	0	0
T90	15183	21	0	0
T93	97886	91	0	0
T95	4744	7	0	0
T104	16253	16	0	0
T107	15873	16	0	0
T111	7885	1	0	0
T146	42210	235	0	0
T147	7713	29	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	2071	0	0
T62	90148	153	0	0
T79	4720	10	0	0
T90	15183	62	0	0
T93	97886	335	0	0
T95	4744	1	0	0
T104	16253	49	0	0
T111	7885	24	0	0
T146	42210	265	0	0
T147	7713	29	0	0
T148	7776	6	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1312	0	0
T62	90148	85	0	0
T79	4720	6	0	0
T90	15183	17	0	0
T93	97886	199	0	0
T104	16253	36	0	0
T107	15873	20	0	0
T111	7885	13	0	0
T146	42210	279	0	0
T147	7713	9	0	0
T148	7776	8	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1246	0	0
T62	90148	66	0	0
T79	4720	11	0	0
T90	15183	32	0	0
T93	97886	119	0	0
T95	4744	9	0	0
T104	16253	20	0	0
T111	7885	9	0	0
T146	42210	293	0	0
T147	7713	10	0	0
T148	7776	1	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1190	0	0
T62	90148	53	0	0
T79	4720	16	0	0
T90	15183	16	0	0
T93	97886	135	0	0
T104	16253	28	0	0
T107	15873	12	0	0
T111	7885	9	0	0
T146	42210	280	0	0
T147	7713	22	0	0
T148	7776	10	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1156	0	0
T62	90148	56	0	0
T79	4720	15	0	0
T90	15183	38	0	0
T93	97886	118	0	0
T104	16253	28	0	0
T107	15873	21	0	0
T111	7885	10	0	0
T146	42210	259	0	0
T147	7713	18	0	0
T148	7776	2	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1231	0	0
T62	90148	47	0	0
T79	4720	8	0	0
T90	15183	27	0	0
T93	97886	114	0	0
T95	4744	4	0	0
T104	16253	15	0	0
T111	7885	14	0	0
T146	42210	232	0	0
T147	7713	25	0	0
T148	7776	4	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1153	0	0
T62	90148	90	0	0
T79	4720	14	0	0
T90	15183	25	0	0
T93	97886	115	0	0
T95	4744	3	0	0
T104	16253	15	0	0
T111	7885	4	0	0
T146	42210	252	0	0
T147	7713	6	0	0
T148	7776	8	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444099894	1296	0	0
T62	90148	60	0	0
T79	4720	21	0	0
T90	15183	22	0	0
T93	97886	110	0	0
T95	4744	5	0	0
T104	16253	22	0	0
T107	15873	28	0	0
T111	7885	10	0	0
T146	42210	250	0	0
T147	7713	20	0	0