Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3903759	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4558565

1

T1

2194

T2

1037

T3

18786

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4674881	1			T1	2618		T2	263		T3	11975
values[0x0]	1893933	1			T1	466		T2	443		T3	9074
values[0x1]	1893510	1			T1	436		T2	464		T3	9015

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2765694	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5696630

1

T1

2461

T2

1066

T3

22142

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	35790	1			T1	16		T2	3		T3	52
valid_sources[0x01]	30683	1			T1	11		T2	3		T3	15
valid_sources[0x02]	33280	1			T1	14		T2	7		T3	184
valid_sources[0x03]	32671	1			T1	10		T2	1		T3	171
valid_sources[0x04]	33635	1			T1	18		T2	7		T3	62
valid_sources[0x05]	30387	1			T1	12		T2	11		T3	245
valid_sources[0x06]	34793	1			T1	21		T3	91		T4	5
valid_sources[0x07]	32297	1			T1	20		T2	3		T3	138
valid_sources[0x08]	34638	1			T1	12		T2	3		T3	88
valid_sources[0x09]	31070	1			T1	10		T2	1		T3	73
valid_sources[0x0a]	31919	1			T1	13		T2	6		T3	125
valid_sources[0x0b]	30947	1			T1	17		T2	4		T3	100
valid_sources[0x0c]	33062	1			T1	9		T2	1		T3	91
valid_sources[0x0d]	30847	1			T1	17		T2	1		T3	156
valid_sources[0x0e]	37589	1			T1	15		T2	3		T3	113
valid_sources[0x0f]	33071	1			T1	16		T2	9		T3	40
valid_sources[0x10]	34219	1			T1	10		T2	5		T3	96
valid_sources[0x11]	33210	1			T1	10		T2	5		T3	248
valid_sources[0x12]	30294	1			T1	20		T2	9		T3	173
valid_sources[0x13]	32926	1			T1	21		T2	2		T3	103
valid_sources[0x14]	33540	1			T1	7		T2	5		T3	119
valid_sources[0x15]	31515	1			T1	7		T2	8		T3	106
valid_sources[0x16]	29016	1			T1	7		T2	6		T3	164
valid_sources[0x17]	31995	1			T1	16		T3	89		T4	1
valid_sources[0x18]	31985	1			T1	11		T2	4		T3	74
valid_sources[0x19]	29673	1			T1	10		T2	5		T3	159
valid_sources[0x1a]	33183	1			T1	12		T2	1		T3	93
valid_sources[0x1b]	31807	1			T1	20		T2	3		T3	180
valid_sources[0x1c]	34498	1			T1	11		T2	1		T3	148
valid_sources[0x1d]	30816	1			T1	9		T2	2		T3	100
valid_sources[0x1e]	33078	1			T1	19		T2	5		T3	174
valid_sources[0x1f]	29798	1			T1	12		T2	7		T3	211
valid_sources[0x20]	31887	1			T1	9		T2	2		T3	106
valid_sources[0x21]	35314	1			T1	16		T2	4		T3	39
valid_sources[0x22]	38658	1			T1	25		T2	2		T3	74
valid_sources[0x23]	40967	1			T1	10		T2	4		T3	166
valid_sources[0x24]	32529	1			T1	11		T2	4		T3	235
valid_sources[0x25]	34236	1			T1	18		T2	10		T3	90
valid_sources[0x26]	37174	1			T1	9		T2	5		T3	147
valid_sources[0x27]	35032	1			T1	17		T2	7		T3	109
valid_sources[0x28]	31456	1			T1	16		T2	1		T3	115
valid_sources[0x29]	31875	1			T1	14		T2	5		T3	184
valid_sources[0x2a]	34551	1			T1	17		T2	4		T3	141
valid_sources[0x2b]	28051	1			T1	9		T3	175		T8	95
valid_sources[0x2c]	34410	1			T1	9		T2	4		T3	100
valid_sources[0x2d]	30237	1			T1	16		T2	3		T3	161
valid_sources[0x2e]	30933	1			T1	5		T2	5		T3	179
valid_sources[0x2f]	31893	1			T1	20		T2	1		T3	120
valid_sources[0x30]	31053	1			T1	11		T2	1		T3	96
valid_sources[0x31]	30411	1			T1	13		T2	4		T3	203
valid_sources[0x32]	29885	1			T1	16		T2	4		T3	129
valid_sources[0x33]	46588	1			T1	10		T2	3		T3	145
valid_sources[0x34]	33591	1			T1	17		T2	4		T3	78
valid_sources[0x35]	32662	1			T1	8		T2	4		T3	54
valid_sources[0x36]	32883	1			T1	14		T2	6		T3	170
valid_sources[0x37]	30662	1			T1	21		T2	7		T3	89
valid_sources[0x38]	30827	1			T1	14		T2	4		T3	96
valid_sources[0x39]	32111	1			T1	19		T2	15		T3	36
valid_sources[0x3a]	35413	1			T1	11		T2	3		T3	62
valid_sources[0x3b]	34604	1			T1	11		T2	5		T3	118
valid_sources[0x3c]	39431	1			T1	9		T2	4		T3	77
valid_sources[0x3d]	32744	1			T1	14		T2	2		T3	91
valid_sources[0x3e]	31026	1			T1	16		T2	5		T3	106
valid_sources[0x3f]	32998	1			T1	16		T2	1		T3	113
valid_sources[0x40]	37674	1			T1	12		T2	3		T3	212
valid_sources[0x41]	31222	1			T1	13		T2	5		T3	105
valid_sources[0x42]	32819	1			T1	16		T2	2		T3	133
valid_sources[0x43]	32354	1			T1	12		T2	4		T3	61
valid_sources[0x44]	31247	1			T1	17		T2	6		T3	32
valid_sources[0x45]	36419	1			T1	10		T2	1		T3	68
valid_sources[0x46]	33513	1			T1	12		T2	14		T3	116
valid_sources[0x47]	31259	1			T1	12		T2	9		T3	39
valid_sources[0x48]	31604	1			T1	15		T2	1		T3	124
valid_sources[0x49]	32257	1			T1	7		T2	2		T3	118
valid_sources[0x4a]	38821	1			T1	16		T2	3		T3	61
valid_sources[0x4b]	31060	1			T1	23		T2	3		T3	82
valid_sources[0x4c]	30877	1			T1	15		T2	4		T3	75
valid_sources[0x4d]	34123	1			T1	9		T2	6		T3	93
valid_sources[0x4e]	32296	1			T1	13		T2	8		T3	121
valid_sources[0x4f]	32196	1			T1	8		T2	8		T3	147
valid_sources[0x50]	33522	1			T1	17		T3	143		T4	2
valid_sources[0x51]	32320	1			T1	15		T2	12		T3	170
valid_sources[0x52]	28378	1			T1	22		T2	10		T3	70
valid_sources[0x53]	29588	1			T1	16		T2	1		T3	48
valid_sources[0x54]	35650	1			T1	11		T2	10		T3	82
valid_sources[0x55]	29205	1			T1	19		T2	1		T3	115
valid_sources[0x56]	33195	1			T1	17		T2	2		T3	205
valid_sources[0x57]	29333	1			T1	21		T2	1		T3	167
valid_sources[0x58]	31937	1			T1	8		T2	5		T3	89
valid_sources[0x59]	30389	1			T1	9		T2	5		T3	93
valid_sources[0x5a]	34436	1			T1	6		T2	5		T3	110
valid_sources[0x5b]	31741	1			T1	18		T2	8		T3	110
valid_sources[0x5c]	36080	1			T1	15		T2	3		T3	225
valid_sources[0x5d]	32624	1			T1	15		T2	4		T3	36
valid_sources[0x5e]	36959	1			T1	14		T2	1		T3	211
valid_sources[0x5f]	32166	1			T1	7		T2	3		T3	96
valid_sources[0x60]	29816	1			T1	19		T2	5		T3	56
valid_sources[0x61]	32441	1			T1	11		T2	3		T3	135
valid_sources[0x62]	31673	1			T1	9		T2	1		T3	44
valid_sources[0x63]	34253	1			T1	12		T2	7		T3	133
valid_sources[0x64]	30555	1			T1	7		T2	10		T3	47
valid_sources[0x65]	34787	1			T1	14		T2	4		T3	128
valid_sources[0x66]	36210	1			T1	10		T2	4		T3	225
valid_sources[0x67]	36422	1			T1	12		T2	6		T3	209
valid_sources[0x68]	32311	1			T1	17		T3	62		T4	2
valid_sources[0x69]	39415	1			T1	10		T2	5		T3	91
valid_sources[0x6a]	31806	1			T1	15		T2	3		T3	49
valid_sources[0x6b]	31567	1			T1	12		T2	5		T3	74
valid_sources[0x6c]	31344	1			T1	13		T2	3		T3	178
valid_sources[0x6d]	32259	1			T1	12		T2	4		T3	150
valid_sources[0x6e]	31625	1			T1	14		T2	2		T3	168
valid_sources[0x6f]	31131	1			T1	10		T3	166		T4	10
valid_sources[0x70]	34840	1			T1	17		T2	3		T3	88
valid_sources[0x71]	38661	1			T1	13		T2	6		T3	104
valid_sources[0x72]	31903	1			T1	19		T2	4		T3	151
valid_sources[0x73]	31365	1			T1	13		T2	2		T3	118
valid_sources[0x74]	32401	1			T1	9		T2	8		T3	60
valid_sources[0x75]	30718	1			T1	17		T2	4		T3	76
valid_sources[0x76]	30396	1			T1	14		T2	1		T3	99
valid_sources[0x77]	33115	1			T1	24		T2	4		T3	153
valid_sources[0x78]	33021	1			T1	22		T2	12		T3	110
valid_sources[0x79]	41780	1			T1	13		T2	9		T3	44
valid_sources[0x7a]	29225	1			T1	8		T2	4		T3	99
valid_sources[0x7b]	33633	1			T1	9		T2	1		T3	103
valid_sources[0x7c]	30213	1			T1	15		T2	4		T3	130
valid_sources[0x7d]	32782	1			T1	9		T2	2		T3	119
valid_sources[0x7e]	35198	1			T1	17		T2	2		T3	209
valid_sources[0x7f]	31241	1			T1	15		T2	8		T3	101
valid_sources[0x80]	30529	1			T1	16		T3	65		T4	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1122379

1

T1

1299

T2

136

T3

2463

values[0x0]

all_enables

biggest_size

1730878

1

T1

466

T2

442

T3

8257

values[0x1]

all_enables

biggest_size

1705308

1

T1

429

T2

459

T3

8066