Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3929802

1

T1

1326

T2

133

T3

11278

full_word

4560160

1

T1

2194

T2

1037

T3

18786

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8489572	1			T1	3520		T2	1170		T3	30064
auto[TlIntgErrCmd]	146	1			T95	13		T96	9		T97	9
auto[TlIntgErrData]	114	1			T95	5		T96	5		T97	8
auto[TlIntgErrBoth]	130	1			T95	12		T96	6		T97	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4681467

1

T1

2618

T2

263

T3

11975

auto[1]

3808495

1

T1

902

T2

907

T3

18089

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3558449	1			T1	1319		T2	127		T3	9512
auto[TlIntgErrNone]	partial	auto[1]	370997	1			T1	7		T2	6		T3	1766
auto[TlIntgErrNone]	full_word	auto[0]	1122843	1			T1	1299		T2	136		T3	2463
auto[TlIntgErrNone]	full_word	auto[1]	3437283	1			T1	895		T2	901		T3	16323
auto[TlIntgErrCmd]	partial	auto[0]	61	1			T95	5		T96	4		T97	1
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T95	6		T96	3		T97	7
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T96	1		T110	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T95	2		T96	1		T97	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T95	3		T96	3		T97	4
auto[TlIntgErrData]	partial	auto[1]	44	1			T95	2		T96	1		T97	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T96	1		T168	1		T170	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T110	1		T171	1		T169	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T95	8		T96	1		T97	1
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T95	4		T96	5		T97	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T172	1		T168	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T97	1		T171	1		T168	1