Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	530098809	3081166	0	0
DepthKnown_A	530098809	529968393	0	0
RvalidKnown_A	530098809	529968393	0	0
WreadyKnown_A	530098809	529968393	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	3081166	0	0
T1	67110	1663	0	0
T2	8706	1663	0	0
T3	106339	12478	0	0
T4	4070	1663	0	0
T5	6535	0	0	0
T6	9490	1663	0	0
T7	238202	14971	0	0
T8	793323	2496	0	0
T9	198341	0	0	0
T10	48537	832	0	0
T12	0	1663	0	0
T13	0	14971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	530098809	3318087	0	0
DepthKnown_A	530098809	529968393	0	0
RvalidKnown_A	530098809	529968393	0	0
WreadyKnown_A	530098809	529968393	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	3318087	0	0
T1	67110	832	0	0
T2	8706	832	0	0
T3	106339	26875	0	0
T4	4070	832	0	0
T5	6535	0	0	0
T6	9490	832	0	0
T7	238202	10816	0	0
T8	793323	2496	0	0
T9	198341	0	0	0
T10	48537	832	0	0
T12	0	832	0	0
T13	0	10816	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	530098809	195069	0	0
DepthKnown_A	530098809	529968393	0	0
RvalidKnown_A	530098809	529968393	0	0
WreadyKnown_A	530098809	529968393	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	195069	0	0
T3	106339	1480	0	0
T4	4070	0	0	0
T5	6535	0	0	0
T6	9490	0	0	0
T7	238202	514	0	0
T8	793323	752	0	0
T9	198341	0	0	0
T10	48537	0	0	0
T11	5738	0	0	0
T13	0	596	0	0
T22	950	0	0	0
T23	0	7	0	0
T26	0	1254	0	0
T27	0	715	0	0
T33	0	128	0	0
T34	0	224	0	0
T35	0	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	530098809	416075	0	0
DepthKnown_A	530098809	529968393	0	0
RvalidKnown_A	530098809	529968393	0	0
WreadyKnown_A	530098809	529968393	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	416075	0	0
T3	106339	4163	0	0
T4	4070	0	0	0
T5	6535	0	0	0
T6	9490	0	0	0
T7	238202	514	0	0
T8	793323	752	0	0
T9	198341	0	0	0
T10	48537	0	0	0
T11	5738	0	0	0
T13	0	596	0	0
T22	950	0	0	0
T23	0	7	0	0
T26	0	1253	0	0
T27	0	714	0	0
T33	0	424	0	0
T34	0	1030	0	0
T35	0	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	530098809	6726090	0	0
DepthKnown_A	530098809	529968393	0	0
RvalidKnown_A	530098809	529968393	0	0
WreadyKnown_A	530098809	529968393	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6726090	0	0
T1	67110	2688	0	0
T2	8706	338	0	0
T3	106339	19050	0	0
T4	4070	122	0	0
T5	6535	316	0	0
T6	9490	313	0	0
T7	238202	4154	0	0
T8	793323	17954	0	0
T9	198341	492	0	0
T10	48537	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	530098809	14790523	0	0
DepthKnown_A	530098809	529968393	0	0
RvalidKnown_A	530098809	529968393	0	0
WreadyKnown_A	530098809	529968393	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	14790523	0	0
T1	67110	2688	0	0
T2	8706	338	0	0
T3	106339	46972	0	0
T4	4070	122	0	0
T5	6535	316	0	0
T6	9490	313	0	0
T7	238202	4154	0	0
T8	793323	17671	0	0
T9	198341	492	0	0
T10	48537	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	529968393	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0