Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T23
1	0	Covered	T3,T8,T23

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Unreachable
1	1	Covered	T3,T8,T23

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	848857466	686731400	0	0
CheckNGreaterZero_A	2862	2862	0	0
GntImpliesReady_A	848857466	3888477	0	0
GntImpliesValid_A	848857466	3888477	0	0
GrantKnown_A	848857466	686731400	0	0
IdxKnown_A	848857466	686731400	0	0
IndexIsCorrect_A	848857466	3888477	0	0
LockArbDecision_A	848857466	0	0	0
NoReadyValidNoGrant_A	848857466	0	0	0
ReadyAndValidImplyGrant_A	848857466	3888477	0	0
ReqAndReadyImplyGrant_A	848857466	3888477	0	0
ReqImpliesValid_A	848857466	3888477	0	0
ReqStaysHighUntilGranted0_M	848857466	0	0	0
RoundRobin_A	848857466	6	0	954
ValidKnown_A	848857466	686731400	0	0
gen_data_port_assertion.DataFlow_A	848857466	3888477	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848857466	686731400	0	0
T1	88200	88127	0	0
T2	13488	12992	0	0
T3	308187	1106592	0	0
T4	4390	4146	0	0
T5	6535	6318	0	0
T6	31740	20068	0	0
T7	1761328	997432	0	0
T8	1574727	1177104	0	0
T9	320135	257592	0	0
T10	65081	56711	0	0
T11	2954	936	0	0
T12	104	104	0	0
T13	849778	845868	0	0
T15	0	50608	0	0
T23	0	2208	0	0
T25	0	55304	0	0
T26	0	114824	0	0
T27	0	113480	0	0
T28	0	79872	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2862	2862	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848857466	3888477	0	0
T1	67110	832	0	0
T2	8706	832	0	0
T3	308187	23646	0	0
T4	4390	832	0	0
T5	6535	0	0	0
T6	31740	832	0	0
T7	1761328	20485	0	0
T8	1574727	9336	0	0
T9	320135	0	0	0
T10	65081	832	0	0
T11	2954	0	0	0
T12	208	832	0	0
T13	1699556	18433	0	0
T15	0	8027	0	0
T23	0	72	0	0
T26	0	7058	0	0
T27	0	4583	0	0
T33	0	987	0	0
T34	0	1594	0	0
T35	0	522	0	0
T45	0	1321	0	0
T46	0	5736	0	0
T47	0	1152	0	0
T48	0	57	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848857466	3888477	0	0
T1	67110	832	0	0
T2	8706	832	0	0
T3	308187	23646	0	0
T4	4390	832	0	0
T5	6535	0	0	0
T6	31740	832	0	0
T7	1761328	20485	0	0
T8	1574727	9336	0	0
T9	320135	0	0	0
T10	65081	832	0	0
T11	2954	0	0	0
T12	208	832	0	0
T13	1699556	18433	0	0
T15	0	8027	0	0
T23	0	72	0	0
T26	0	7058	0	0
T27	0	4583	0	0
T33	0	987	0	0
T34	0	1594	0	0
T35	0	522	0	0
T45	0	1321	0	0
T46	0	5736	0	0
T47	0	1152	0	0
T48	0	57	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848857466	686731400	0	0
T1	88200	88127	0	0
T2	13488	12992	0	0
T3	308187	1106592	0	0
T4	4390	4146	0	0
T5	6535	6318	0	0
T6	31740	20068	0	0
T7	1761328	997432	0	0
T8	1574727	1177104	0	0
T9	320135	257592	0	0
T10	65081	56711	0	0
T11	2954	936	0	0
T12	104	104	0	0
T13	849778	845868	0	0
T15	0	50608	0	0
T23	0	2208	0	0
T25	0	55304	0	0
T26	0	114824	0	0
T27	0	113480	0	0
T28	0	79872	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848857466	686731400	0	0
T1	88200	88127	0	0
T2	13488	12992	0	0
T3	308187	1106592	0	0
T4	4390	4146	0	0
T5	6535	6318	0	0
T6	31740	20068	0	0
T7	1761328	997432	0	0
T8	1574727	1177104	0	0
T9	320135	257592	0	0
T10	65081	56711	0	0
T11	2954	936	0	0
T12	104	104	0	0
T13	849778	845868	0	0
T15	0	50608	0	0
T23	0	2208	0	0
T25	0	55304	0	0
T26	0	114824	0	0
T27	0	113480	0	0
T28	0	79872	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848857466	3888477	0	0
T1	67110	832	0	0
T2	8706	832	0	0
T3	308187	23646	0	0
T4	4390	832	0	0
T5	6535	0	0	0
T6	31740	832	0	0
T7	1761328	20485	0	0
T8	1574727	9336	0	0
T9	320135	0	0	0
T10	65081	832	0	0
T11	2954	0	0	0
T12	208	832	0	0
T13	1699556	18433	0	0
T15	0	8027	0	0
T23	0	72	0	0
T26	0	7058	0	0
T27	0	4583	0	0
T33	0	987	0	0
T34	0	1594	0	0
T35	0	522	0	0
T45	0	1321	0	0
T46	0	5736	0	0
T47	0	1152	0	0
T48	0	57	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848857466	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848857466	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848857466	3888477	0	0
T1	67110	832	0	0
T2	8706	832	0	0
T3	308187	23646	0	0
T4	4390	832	0	0
T5	6535	0	0	0
T6	31740	832	0	0
T7	1761328	20485	0	0
T8	1574727	9336	0	0
T9	320135	0	0	0
T10	65081	832	0	0
T11	2954	0	0	0
T12	208	832	0	0
T13	1699556	18433	0	0
T15	0	8027	0	0
T23	0	72	0	0
T26	0	7058	0	0
T27	0	4583	0	0
T33	0	987	0	0
T34	0	1594	0	0
T35	0	522	0	0
T45	0	1321	0	0
T46	0	5736	0	0
T47	0	1152	0	0
T48	0	57	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848857466	3888477	0	0
T1	67110	832	0	0
T2	8706	832	0	0
T3	308187	23646	0	0
T4	4390	832	0	0
T5	6535	0	0	0
T6	31740	832	0	0
T7	1761328	20485	0	0
T8	1574727	9336	0	0
T9	320135	0	0	0
T10	65081	832	0	0
T11	2954	0	0	0
T12	208	832	0	0
T13	1699556	18433	0	0
T15	0	8027	0	0
T23	0	72	0	0
T26	0	7058	0	0
T27	0	4583	0	0
T33	0	987	0	0
T34	0	1594	0	0
T35	0	522	0	0
T45	0	1321	0	0
T46	0	5736	0	0
T47	0	1152	0	0
T48	0	57	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848857466	3888477	0	0
T1	67110	832	0	0
T2	8706	832	0	0
T3	308187	23646	0	0
T4	4390	832	0	0
T5	6535	0	0	0
T6	31740	832	0	0
T7	1761328	20485	0	0
T8	1574727	9336	0	0
T9	320135	0	0	0
T10	65081	832	0	0
T11	2954	0	0	0
T12	208	832	0	0
T13	1699556	18433	0	0
T15	0	8027	0	0
T23	0	72	0	0
T26	0	7058	0	0
T27	0	4583	0	0
T33	0	987	0	0
T34	0	1594	0	0
T35	0	522	0	0
T45	0	1321	0	0
T46	0	5736	0	0
T47	0	1152	0	0
T48	0	57	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	848857466	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848857466	6	0	954
T30	283931	1	0	1
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	498393	0	0	1
T55	254370	0	0	1
T56	55972	0	0	1
T57	77751	0	0	1
T58	115795	0	0	1
T59	90492	0	0	1
T60	6551	0	0	1
T61	5802	0	0	1
T62	1287	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848857466	686731400	0	0
T1	88200	88127	0	0
T2	13488	12992	0	0
T3	308187	1106592	0	0
T4	4390	4146	0	0
T5	6535	6318	0	0
T6	31740	20068	0	0
T7	1761328	997432	0	0
T8	1574727	1177104	0	0
T9	320135	257592	0	0
T10	65081	56711	0	0
T11	2954	936	0	0
T12	104	104	0	0
T13	849778	845868	0	0
T15	0	50608	0	0
T23	0	2208	0	0
T25	0	55304	0	0
T26	0	114824	0	0
T27	0	113480	0	0
T28	0	79872	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848857466	3888477	0	0
T1	67110	832	0	0
T2	8706	832	0	0
T3	308187	23646	0	0
T4	4390	832	0	0
T5	6535	0	0	0
T6	31740	832	0	0
T7	1761328	20485	0	0
T8	1574727	9336	0	0
T9	320135	0	0	0
T10	65081	832	0	0
T11	2954	0	0	0
T12	208	832	0	0
T13	1699556	18433	0	0
T15	0	8027	0	0
T23	0	72	0	0
T26	0	7058	0	0
T27	0	4583	0	0
T33	0	987	0	0
T34	0	1594	0	0
T35	0	522	0	0
T45	0	1321	0	0
T46	0	5736	0	0
T47	0	1152	0	0
T48	0	57	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T23
1	0	Covered	T3,T8,T23

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Unreachable
1	1	Covered	T3,T8,T23

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T8,T23
0	0	1	Unreachable
0	0	0	Covered	T3,T8,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	160620105	26694953	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	160620105	611715	0	0
GntImpliesValid_A	160620105	611715	0	0
GrantKnown_A	160620105	26694953	0	0
IdxKnown_A	160620105	26694953	0	0
IndexIsCorrect_A	160620105	611715	0	0
LockArbDecision_A	160620105	0	0	0
NoReadyValidNoGrant_A	160620105	0	0	0
ReadyAndValidImplyGrant_A	160620105	611715	0	0
ReqAndReadyImplyGrant_A	160620105	611715	0	0
ReqImpliesValid_A	160620105	611715	0	0
ReqStaysHighUntilGranted0_M	160620105	0	0	0
RoundRobin_A	160620105	0	0	0
ValidKnown_A	160620105	26694953	0	0
gen_data_port_assertion.DataFlow_A	160620105	611715	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	26694953	0	0
T3	100924	153336	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	0	0	0
T8	390702	131056	0	0
T9	60897	59336	0	0
T10	8272	0	0	0
T11	1477	936	0	0
T12	104	0	0	0
T13	849778	0	0	0
T15	0	50608	0	0
T23	0	2208	0	0
T25	0	55304	0	0
T26	0	114824	0	0
T27	0	113480	0	0
T28	0	79872	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	611715	0	0
T3	100924	4057	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	0	0	0
T8	390702	4575	0	0
T9	60897	0	0	0
T10	8272	0	0	0
T11	1477	0	0	0
T12	104	0	0	0
T13	849778	0	0	0
T15	0	2065	0	0
T23	0	72	0	0
T26	0	3884	0	0
T27	0	4465	0	0
T45	0	1321	0	0
T46	0	5736	0	0
T47	0	1152	0	0
T48	0	57	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	611715	0	0
T3	100924	4057	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	0	0	0
T8	390702	4575	0	0
T9	60897	0	0	0
T10	8272	0	0	0
T11	1477	0	0	0
T12	104	0	0	0
T13	849778	0	0	0
T15	0	2065	0	0
T23	0	72	0	0
T26	0	3884	0	0
T27	0	4465	0	0
T45	0	1321	0	0
T46	0	5736	0	0
T47	0	1152	0	0
T48	0	57	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	26694953	0	0
T3	100924	153336	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	0	0	0
T8	390702	131056	0	0
T9	60897	59336	0	0
T10	8272	0	0	0
T11	1477	936	0	0
T12	104	0	0	0
T13	849778	0	0	0
T15	0	50608	0	0
T23	0	2208	0	0
T25	0	55304	0	0
T26	0	114824	0	0
T27	0	113480	0	0
T28	0	79872	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	26694953	0	0
T3	100924	153336	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	0	0	0
T8	390702	131056	0	0
T9	60897	59336	0	0
T10	8272	0	0	0
T11	1477	936	0	0
T12	104	0	0	0
T13	849778	0	0	0
T15	0	50608	0	0
T23	0	2208	0	0
T25	0	55304	0	0
T26	0	114824	0	0
T27	0	113480	0	0
T28	0	79872	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	611715	0	0
T3	100924	4057	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	0	0	0
T8	390702	4575	0	0
T9	60897	0	0	0
T10	8272	0	0	0
T11	1477	0	0	0
T12	104	0	0	0
T13	849778	0	0	0
T15	0	2065	0	0
T23	0	72	0	0
T26	0	3884	0	0
T27	0	4465	0	0
T45	0	1321	0	0
T46	0	5736	0	0
T47	0	1152	0	0
T48	0	57	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	611715	0	0
T3	100924	4057	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	0	0	0
T8	390702	4575	0	0
T9	60897	0	0	0
T10	8272	0	0	0
T11	1477	0	0	0
T12	104	0	0	0
T13	849778	0	0	0
T15	0	2065	0	0
T23	0	72	0	0
T26	0	3884	0	0
T27	0	4465	0	0
T45	0	1321	0	0
T46	0	5736	0	0
T47	0	1152	0	0
T48	0	57	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	611715	0	0
T3	100924	4057	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	0	0	0
T8	390702	4575	0	0
T9	60897	0	0	0
T10	8272	0	0	0
T11	1477	0	0	0
T12	104	0	0	0
T13	849778	0	0	0
T15	0	2065	0	0
T23	0	72	0	0
T26	0	3884	0	0
T27	0	4465	0	0
T45	0	1321	0	0
T46	0	5736	0	0
T47	0	1152	0	0
T48	0	57	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	611715	0	0
T3	100924	4057	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	0	0	0
T8	390702	4575	0	0
T9	60897	0	0	0
T10	8272	0	0	0
T11	1477	0	0	0
T12	104	0	0	0
T13	849778	0	0	0
T15	0	2065	0	0
T23	0	72	0	0
T26	0	3884	0	0
T27	0	4465	0	0
T45	0	1321	0	0
T46	0	5736	0	0
T47	0	1152	0	0
T48	0	57	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	26694953	0	0
T3	100924	153336	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	0	0	0
T8	390702	131056	0	0
T9	60897	59336	0	0
T10	8272	0	0	0
T11	1477	936	0	0
T12	104	0	0	0
T13	849778	0	0	0
T15	0	50608	0	0
T23	0	2208	0	0
T25	0	55304	0	0
T26	0	114824	0	0
T27	0	113480	0	0
T28	0	79872	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	611715	0	0
T3	100924	4057	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	0	0	0
T8	390702	4575	0	0
T9	60897	0	0	0
T10	8272	0	0	0
T11	1477	0	0	0
T12	104	0	0	0
T13	849778	0	0	0
T15	0	2065	0	0
T23	0	72	0	0
T26	0	3884	0	0
T27	0	4465	0	0
T45	0	1321	0	0
T46	0	5736	0	0
T47	0	1152	0	0
T48	0	57	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T7,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	160620105	132505720	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	160620105	876404	0	0
GntImpliesValid_A	160620105	876404	0	0
GrantKnown_A	160620105	132505720	0	0
IdxKnown_A	160620105	132505720	0	0
IndexIsCorrect_A	160620105	876404	0	0
LockArbDecision_A	160620105	0	0	0
NoReadyValidNoGrant_A	160620105	0	0	0
ReadyAndValidImplyGrant_A	160620105	876404	0	0
ReqAndReadyImplyGrant_A	160620105	876404	0	0
ReqImpliesValid_A	160620105	876404	0	0
ReqStaysHighUntilGranted0_M	160620105	0	0	0
RoundRobin_A	160620105	0	0	0
ValidKnown_A	160620105	132505720	0	0
gen_data_port_assertion.DataFlow_A	160620105	876404	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	132505720	0	0
T1	21090	21090	0	0
T2	4782	4336	0	0
T3	100924	846925	0	0
T4	160	160	0	0
T6	11125	10654	0	0
T7	761563	759235	0	0
T8	390702	252797	0	0
T9	60897	0	0	0
T10	8272	8272	0	0
T11	1477	0	0	0
T12	0	104	0	0
T13	0	845868	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	876404	0	0
T3	100924	6341	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	9126	0	0
T8	390702	7	0	0
T9	60897	0	0	0
T10	8272	0	0	0
T11	1477	0	0	0
T12	104	0	0	0
T13	849778	6990	0	0
T15	0	5962	0	0
T26	0	3174	0	0
T27	0	118	0	0
T33	0	987	0	0
T34	0	1594	0	0
T35	0	522	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	876404	0	0
T3	100924	6341	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	9126	0	0
T8	390702	7	0	0
T9	60897	0	0	0
T10	8272	0	0	0
T11	1477	0	0	0
T12	104	0	0	0
T13	849778	6990	0	0
T15	0	5962	0	0
T26	0	3174	0	0
T27	0	118	0	0
T33	0	987	0	0
T34	0	1594	0	0
T35	0	522	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	132505720	0	0
T1	21090	21090	0	0
T2	4782	4336	0	0
T3	100924	846925	0	0
T4	160	160	0	0
T6	11125	10654	0	0
T7	761563	759235	0	0
T8	390702	252797	0	0
T9	60897	0	0	0
T10	8272	8272	0	0
T11	1477	0	0	0
T12	0	104	0	0
T13	0	845868	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	132505720	0	0
T1	21090	21090	0	0
T2	4782	4336	0	0
T3	100924	846925	0	0
T4	160	160	0	0
T6	11125	10654	0	0
T7	761563	759235	0	0
T8	390702	252797	0	0
T9	60897	0	0	0
T10	8272	8272	0	0
T11	1477	0	0	0
T12	0	104	0	0
T13	0	845868	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	876404	0	0
T3	100924	6341	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	9126	0	0
T8	390702	7	0	0
T9	60897	0	0	0
T10	8272	0	0	0
T11	1477	0	0	0
T12	104	0	0	0
T13	849778	6990	0	0
T15	0	5962	0	0
T26	0	3174	0	0
T27	0	118	0	0
T33	0	987	0	0
T34	0	1594	0	0
T35	0	522	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	876404	0	0
T3	100924	6341	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	9126	0	0
T8	390702	7	0	0
T9	60897	0	0	0
T10	8272	0	0	0
T11	1477	0	0	0
T12	104	0	0	0
T13	849778	6990	0	0
T15	0	5962	0	0
T26	0	3174	0	0
T27	0	118	0	0
T33	0	987	0	0
T34	0	1594	0	0
T35	0	522	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	876404	0	0
T3	100924	6341	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	9126	0	0
T8	390702	7	0	0
T9	60897	0	0	0
T10	8272	0	0	0
T11	1477	0	0	0
T12	104	0	0	0
T13	849778	6990	0	0
T15	0	5962	0	0
T26	0	3174	0	0
T27	0	118	0	0
T33	0	987	0	0
T34	0	1594	0	0
T35	0	522	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	876404	0	0
T3	100924	6341	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	9126	0	0
T8	390702	7	0	0
T9	60897	0	0	0
T10	8272	0	0	0
T11	1477	0	0	0
T12	104	0	0	0
T13	849778	6990	0	0
T15	0	5962	0	0
T26	0	3174	0	0
T27	0	118	0	0
T33	0	987	0	0
T34	0	1594	0	0
T35	0	522	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	132505720	0	0
T1	21090	21090	0	0
T2	4782	4336	0	0
T3	100924	846925	0	0
T4	160	160	0	0
T6	11125	10654	0	0
T7	761563	759235	0	0
T8	390702	252797	0	0
T9	60897	0	0	0
T10	8272	8272	0	0
T11	1477	0	0	0
T12	0	104	0	0
T13	0	845868	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160620105	876404	0	0
T3	100924	6341	0	0
T4	160	0	0	0
T6	11125	0	0	0
T7	761563	9126	0	0
T8	390702	7	0	0
T9	60897	0	0	0
T10	8272	0	0	0
T11	1477	0	0	0
T12	104	0	0	0
T13	849778	6990	0	0
T15	0	5962	0	0
T26	0	3174	0	0
T27	0	118	0	0
T33	0	987	0	0
T34	0	1594	0	0
T35	0	522	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	527617256	527530727	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	527617256	2400358	0	0
GntImpliesValid_A	527617256	2400358	0	0
GrantKnown_A	527617256	527530727	0	0
IdxKnown_A	527617256	527530727	0	0
IndexIsCorrect_A	527617256	2400358	0	0
LockArbDecision_A	527617256	0	0	0
NoReadyValidNoGrant_A	527617256	0	0	0
ReadyAndValidImplyGrant_A	527617256	2400358	0	0
ReqAndReadyImplyGrant_A	527617256	2400358	0	0
ReqImpliesValid_A	527617256	2400358	0	0
ReqStaysHighUntilGranted0_M	527617256	0	0	0
RoundRobin_A	527617256	6	0	954
ValidKnown_A	527617256	527530727	0	0
gen_data_port_assertion.DataFlow_A	527617256	2400358	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527617256	527530727	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527617256	2400358	0	0
T1	67110	832	0	0
T2	8706	832	0	0
T3	106339	13248	0	0
T4	4070	832	0	0
T5	6535	0	0	0
T6	9490	832	0	0
T7	238202	11359	0	0
T8	793323	4754	0	0
T9	198341	0	0	0
T10	48537	832	0	0
T12	0	832	0	0
T13	0	11443	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527617256	2400358	0	0
T1	67110	832	0	0
T2	8706	832	0	0
T3	106339	13248	0	0
T4	4070	832	0	0
T5	6535	0	0	0
T6	9490	832	0	0
T7	238202	11359	0	0
T8	793323	4754	0	0
T9	198341	0	0	0
T10	48537	832	0	0
T12	0	832	0	0
T13	0	11443	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527617256	527530727	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527617256	527530727	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527617256	2400358	0	0
T1	67110	832	0	0
T2	8706	832	0	0
T3	106339	13248	0	0
T4	4070	832	0	0
T5	6535	0	0	0
T6	9490	832	0	0
T7	238202	11359	0	0
T8	793323	4754	0	0
T9	198341	0	0	0
T10	48537	832	0	0
T12	0	832	0	0
T13	0	11443	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527617256	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527617256	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527617256	2400358	0	0
T1	67110	832	0	0
T2	8706	832	0	0
T3	106339	13248	0	0
T4	4070	832	0	0
T5	6535	0	0	0
T6	9490	832	0	0
T7	238202	11359	0	0
T8	793323	4754	0	0
T9	198341	0	0	0
T10	48537	832	0	0
T12	0	832	0	0
T13	0	11443	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527617256	2400358	0	0
T1	67110	832	0	0
T2	8706	832	0	0
T3	106339	13248	0	0
T4	4070	832	0	0
T5	6535	0	0	0
T6	9490	832	0	0
T7	238202	11359	0	0
T8	793323	4754	0	0
T9	198341	0	0	0
T10	48537	832	0	0
T12	0	832	0	0
T13	0	11443	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527617256	2400358	0	0
T1	67110	832	0	0
T2	8706	832	0	0
T3	106339	13248	0	0
T4	4070	832	0	0
T5	6535	0	0	0
T6	9490	832	0	0
T7	238202	11359	0	0
T8	793323	4754	0	0
T9	198341	0	0	0
T10	48537	832	0	0
T12	0	832	0	0
T13	0	11443	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	527617256	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527617256	6	0	954
T30	283931	1	0	1
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	498393	0	0	1
T55	254370	0	0	1
T56	55972	0	0	1
T57	77751	0	0	1
T58	115795	0	0	1
T59	90492	0	0	1
T60	6551	0	0	1
T61	5802	0	0	1
T62	1287	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527617256	527530727	0	0
T1	67110	67037	0	0
T2	8706	8656	0	0
T3	106339	106331	0	0
T4	4070	3986	0	0
T5	6535	6318	0	0
T6	9490	9414	0	0
T7	238202	238197	0	0
T8	793323	793251	0	0
T9	198341	198256	0	0
T10	48537	48439	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527617256	2400358	0	0
T1	67110	832	0	0
T2	8706	832	0	0
T3	106339	13248	0	0
T4	4070	832	0	0
T5	6535	0	0	0
T6	9490	832	0	0
T7	238202	11359	0	0
T8	793323	4754	0	0
T9	198341	0	0	0
T10	48537	832	0	0
T12	0	832	0	0
T13	0	11443	0	0