Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	530098809	3309	0	0
addr_swap_data_rd_A	530098809	2529	0	0
addr_swap_mask_rd_A	530098809	2634	0	0
cfg_rd_A	530098809	3225	0	0
cmd_filter_0_rd_A	530098809	13752	0	0
cmd_filter_1_rd_A	530098809	12648	0	0
cmd_filter_2_rd_A	530098809	12750	0	0
cmd_filter_3_rd_A	530098809	13323	0	0
cmd_filter_4_rd_A	530098809	14257	0	0
cmd_filter_5_rd_A	530098809	12056	0	0
cmd_filter_6_rd_A	530098809	13803	0	0
cmd_filter_7_rd_A	530098809	11726	0	0
cmd_info_0_rd_A	530098809	6806	0	0
cmd_info_10_rd_A	530098809	6520	0	0
cmd_info_11_rd_A	530098809	7302	0	0
cmd_info_12_rd_A	530098809	6511	0	0
cmd_info_13_rd_A	530098809	7363	0	0
cmd_info_14_rd_A	530098809	6914	0	0
cmd_info_15_rd_A	530098809	6551	0	0
cmd_info_16_rd_A	530098809	6788	0	0
cmd_info_17_rd_A	530098809	6640	0	0
cmd_info_18_rd_A	530098809	6288	0	0
cmd_info_19_rd_A	530098809	6865	0	0
cmd_info_1_rd_A	530098809	6677	0	0
cmd_info_20_rd_A	530098809	6742	0	0
cmd_info_21_rd_A	530098809	6547	0	0
cmd_info_22_rd_A	530098809	6585	0	0
cmd_info_23_rd_A	530098809	6748	0	0
cmd_info_2_rd_A	530098809	6774	0	0
cmd_info_3_rd_A	530098809	6573	0	0
cmd_info_4_rd_A	530098809	6935	0	0
cmd_info_5_rd_A	530098809	6716	0	0
cmd_info_6_rd_A	530098809	6595	0	0
cmd_info_7_rd_A	530098809	5937	0	0
cmd_info_8_rd_A	530098809	5914	0	0
cmd_info_9_rd_A	530098809	6234	0	0
cmd_info_en4b_rd_A	530098809	2825	0	0
cmd_info_ex4b_rd_A	530098809	2770	0	0
cmd_info_wrdi_rd_A	530098809	3095	0	0
cmd_info_wren_rd_A	530098809	3157	0	0
intercept_en_rd_A	530098809	3601	0	0
intr_enable_rd_A	530098809	5236	0	0
jedec_cc_rd_A	530098809	2881	0	0
jedec_id_rd_A	530098809	2901	0	0
mailbox_addr_rd_A	530098809	2512	0	0
payload_swap_data_rd_A	530098809	2762	0	0
payload_swap_mask_rd_A	530098809	2561	0	0
read_threshold_rd_A	530098809	2727	0	0
tpm_access_0_rd_A	530098809	3454	0	0
tpm_access_1_rd_A	530098809	2550	0	0
tpm_cfg_rd_A	530098809	3915	0	0
tpm_did_vid_rd_A	530098809	2871	0	0
tpm_int_enable_rd_A	530098809	2695	0	0
tpm_int_status_rd_A	530098809	2573	0	0
tpm_int_vector_rd_A	530098809	2673	0	0
tpm_intf_capability_rd_A	530098809	2723	0	0
tpm_rid_rd_A	530098809	2585	0	0
tpm_sts_rd_A	530098809	2565	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	3309	0	0
T66	15430	7	0	0
T68	4120	2	0	0
T92	6660	64	0	0
T93	5776	248	0	0
T94	15409	202	0	0
T95	97674	2	0	0
T96	66789	2	0	0
T97	19728	3	0	0
T108	8545	6	0	0
T110	30004	3	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2529	0	0
T66	15430	25	0	0
T78	4352	10	0	0
T95	97674	42	0	0
T96	66789	62	0	0
T115	3819	3	0	0
T124	234395	405	0	0
T145	6240	24	0	0
T146	7044	3	0	0
T147	20158	30	0	0
T148	78985	104	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2634	0	0
T66	15430	14	0	0
T78	4352	8	0	0
T95	97674	75	0	0
T96	66789	68	0	0
T115	3819	9	0	0
T124	234395	400	0	0
T145	6240	18	0	0
T146	7044	10	0	0
T147	20158	55	0	0
T148	78985	107	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	3225	0	0
T66	15430	16	0	0
T78	4352	6	0	0
T95	97674	119	0	0
T96	66789	148	0	0
T115	3819	14	0	0
T124	234395	454	0	0
T145	6240	7	0	0
T146	7044	4	0	0
T147	20158	45	0	0
T148	78985	159	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	13752	0	0
T66	15430	294	0	0
T78	4352	10	0	0
T95	97674	1462	0	0
T96	66789	1495	0	0
T115	3819	129	0	0
T124	234395	403	0	0
T145	6240	12	0	0
T146	7044	5	0	0
T147	20158	63	0	0
T148	78985	140	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	12648	0	0
T66	15430	157	0	0
T78	4352	5	0	0
T95	97674	904	0	0
T96	66789	1286	0	0
T115	3819	130	0	0
T124	234395	386	0	0
T145	6240	25	0	0
T146	7044	12	0	0
T147	20158	51	0	0
T148	78985	93	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	12750	0	0
T66	15430	141	0	0
T78	4352	19	0	0
T95	97674	904	0	0
T96	66789	1015	0	0
T112	61905	624	0	0
T124	234395	416	0	0
T145	6240	24	0	0
T146	7044	26	0	0
T147	20158	52	0	0
T148	78985	157	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	13323	0	0
T66	15430	23	0	0
T78	4352	18	0	0
T95	97674	1235	0	0
T96	66789	693	0	0
T115	3819	123	0	0
T124	234395	429	0	0
T145	6240	9	0	0
T146	7044	5	0	0
T147	20158	65	0	0
T148	78985	102	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	14257	0	0
T66	15430	17	0	0
T78	4352	17	0	0
T95	97674	1218	0	0
T96	66789	1528	0	0
T112	61905	860	0	0
T124	234395	419	0	0
T145	6240	13	0	0
T147	20158	84	0	0
T148	78985	143	0	0
T149	19044	11	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	12056	0	0
T66	15430	207	0	0
T78	4352	3	0	0
T95	97674	948	0	0
T96	66789	1060	0	0
T115	3819	3	0	0
T124	234395	346	0	0
T145	6240	18	0	0
T146	7044	12	0	0
T147	20158	64	0	0
T148	78985	97	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	13803	0	0
T66	15430	378	0	0
T78	4352	11	0	0
T95	97674	1087	0	0
T96	66789	1238	0	0
T115	3819	126	0	0
T124	234395	430	0	0
T145	6240	10	0	0
T146	7044	5	0	0
T147	20158	115	0	0
T148	78985	123	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	11726	0	0
T66	15430	102	0	0
T78	4352	11	0	0
T95	97674	1014	0	0
T96	66789	1299	0	0
T112	61905	688	0	0
T115	3819	9	0	0
T124	234395	418	0	0
T145	6240	9	0	0
T147	20158	43	0	0
T148	78985	109	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6806	0	0
T66	15430	92	0	0
T78	4352	12	0	0
T95	97674	540	0	0
T96	66789	673	0	0
T115	3819	1	0	0
T124	234395	291	0	0
T145	6240	1	0	0
T146	7044	14	0	0
T147	20158	34	0	0
T148	78985	148	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6520	0	0
T66	15430	72	0	0
T78	4352	16	0	0
T95	97674	499	0	0
T96	66789	596	0	0
T112	61905	375	0	0
T124	234395	380	0	0
T145	6240	12	0	0
T146	7044	17	0	0
T147	20158	76	0	0
T148	78985	131	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	7302	0	0
T66	15430	112	0	0
T78	4352	5	0	0
T95	97674	532	0	0
T96	66789	438	0	0
T115	3819	45	0	0
T124	234395	405	0	0
T145	6240	14	0	0
T146	7044	25	0	0
T147	20158	75	0	0
T148	78985	140	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6511	0	0
T66	15430	111	0	0
T78	4352	10	0	0
T95	97674	323	0	0
T96	66789	457	0	0
T115	3819	1	0	0
T124	234395	325	0	0
T145	6240	15	0	0
T146	7044	12	0	0
T147	20158	72	0	0
T148	78985	142	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	7363	0	0
T66	15430	110	0	0
T78	4352	17	0	0
T95	97674	434	0	0
T96	66789	809	0	0
T112	61905	312	0	0
T115	3819	2	0	0
T124	234395	439	0	0
T146	7044	6	0	0
T147	20158	64	0	0
T148	78985	169	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6914	0	0
T66	15430	81	0	0
T78	4352	5	0	0
T95	97674	432	0	0
T96	66789	605	0	0
T112	61905	316	0	0
T124	234395	481	0	0
T145	6240	29	0	0
T146	7044	10	0	0
T147	20158	69	0	0
T148	78985	115	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6551	0	0
T66	15430	66	0	0
T78	4352	20	0	0
T95	97674	344	0	0
T96	66789	599	0	0
T112	61905	359	0	0
T115	3819	9	0	0
T124	234395	350	0	0
T145	6240	11	0	0
T147	20158	69	0	0
T148	78985	117	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6788	0	0
T66	15430	88	0	0
T78	4352	9	0	0
T95	97674	414	0	0
T96	66789	602	0	0
T112	61905	304	0	0
T115	3819	8	0	0
T124	234395	378	0	0
T146	7044	15	0	0
T147	20158	17	0	0
T148	78985	118	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6640	0	0
T66	15430	105	0	0
T78	4352	8	0	0
T95	97674	377	0	0
T96	66789	380	0	0
T115	3819	56	0	0
T124	234395	385	0	0
T145	6240	12	0	0
T146	7044	27	0	0
T147	20158	78	0	0
T148	78985	176	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6288	0	0
T66	15430	161	0	0
T78	4352	14	0	0
T95	97674	341	0	0
T96	66789	525	0	0
T115	3819	47	0	0
T124	234395	401	0	0
T145	6240	2	0	0
T146	7044	9	0	0
T147	20158	43	0	0
T148	78985	99	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6865	0	0
T66	15430	25	0	0
T78	4352	12	0	0
T95	97674	485	0	0
T96	66789	717	0	0
T115	3819	1	0	0
T124	234395	490	0	0
T145	6240	14	0	0
T146	7044	8	0	0
T147	20158	39	0	0
T148	78985	70	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6677	0	0
T66	15430	151	0	0
T78	4352	17	0	0
T95	97674	493	0	0
T96	66789	575	0	0
T115	3819	3	0	0
T124	234395	330	0	0
T145	6240	9	0	0
T146	7044	15	0	0
T147	20158	70	0	0
T148	78985	160	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6742	0	0
T66	15430	111	0	0
T78	4352	7	0	0
T95	97674	575	0	0
T96	66789	618	0	0
T115	3819	1	0	0
T124	234395	366	0	0
T145	6240	10	0	0
T146	7044	32	0	0
T147	20158	20	0	0
T148	78985	134	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6547	0	0
T66	15430	73	0	0
T78	4352	8	0	0
T95	97674	447	0	0
T96	66789	404	0	0
T112	61905	254	0	0
T115	3819	50	0	0
T124	234395	413	0	0
T146	7044	16	0	0
T147	20158	22	0	0
T148	78985	134	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6585	0	0
T66	15430	86	0	0
T78	4352	9	0	0
T95	97674	447	0	0
T96	66789	532	0	0
T112	61905	343	0	0
T115	3819	62	0	0
T124	234395	441	0	0
T146	7044	24	0	0
T147	20158	69	0	0
T148	78985	182	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6748	0	0
T66	15430	108	0	0
T78	4352	5	0	0
T95	97674	332	0	0
T96	66789	559	0	0
T115	3819	33	0	0
T124	234395	352	0	0
T145	6240	19	0	0
T146	7044	8	0	0
T147	20158	76	0	0
T148	78985	121	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6774	0	0
T66	15430	171	0	0
T78	4352	17	0	0
T95	97674	429	0	0
T96	66789	642	0	0
T115	3819	61	0	0
T124	234395	383	0	0
T145	6240	34	0	0
T146	7044	6	0	0
T147	20158	56	0	0
T148	78985	108	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6573	0	0
T66	15430	66	0	0
T78	4352	9	0	0
T95	97674	496	0	0
T96	66789	551	0	0
T115	3819	38	0	0
T124	234395	478	0	0
T145	6240	3	0	0
T146	7044	2	0	0
T147	20158	46	0	0
T148	78985	144	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6935	0	0
T66	15430	140	0	0
T78	4352	17	0	0
T95	97674	449	0	0
T96	66789	666	0	0
T112	61905	264	0	0
T115	3819	7	0	0
T124	234395	387	0	0
T146	7044	8	0	0
T147	20158	43	0	0
T148	78985	103	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6716	0	0
T66	15430	88	0	0
T78	4352	7	0	0
T95	97674	471	0	0
T96	66789	512	0	0
T112	61905	273	0	0
T124	234395	376	0	0
T145	6240	13	0	0
T147	20158	68	0	0
T148	78985	150	0	0
T149	19044	51	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6595	0	0
T66	15430	73	0	0
T78	4352	11	0	0
T95	97674	437	0	0
T96	66789	524	0	0
T112	61905	317	0	0
T124	234395	441	0	0
T145	6240	11	0	0
T147	20158	56	0	0
T148	78985	118	0	0
T149	19044	9	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	5937	0	0
T66	15430	138	0	0
T78	4352	13	0	0
T95	97674	406	0	0
T96	66789	353	0	0
T112	61905	208	0	0
T115	3819	6	0	0
T124	234395	483	0	0
T146	7044	8	0	0
T147	20158	102	0	0
T148	78985	117	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	5914	0	0
T66	15430	83	0	0
T78	4352	6	0	0
T94	15409	1	0	0
T95	97674	308	0	0
T96	66789	449	0	0
T115	3819	3	0	0
T124	234395	375	0	0
T145	6240	4	0	0
T147	20158	48	0	0
T148	78985	103	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	6234	0	0
T66	15430	23	0	0
T78	4352	15	0	0
T95	97674	493	0	0
T96	66789	564	0	0
T112	61905	255	0	0
T115	3819	8	0	0
T124	234395	370	0	0
T146	7044	11	0	0
T147	20158	40	0	0
T148	78985	118	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2825	0	0
T66	15430	19	0	0
T78	4352	15	0	0
T95	97674	132	0	0
T96	66789	84	0	0
T112	61905	82	0	0
T115	3819	12	0	0
T124	234395	395	0	0
T146	7044	1	0	0
T147	20158	90	0	0
T148	78985	120	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2770	0	0
T66	15430	21	0	0
T78	4352	14	0	0
T95	97674	58	0	0
T96	66789	124	0	0
T115	3819	7	0	0
T124	234395	361	0	0
T145	6240	2	0	0
T146	7044	12	0	0
T147	20158	47	0	0
T148	78985	144	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	3095	0	0
T66	15430	34	0	0
T78	4352	14	0	0
T95	97674	87	0	0
T96	66789	115	0	0
T115	3819	4	0	0
T124	234395	377	0	0
T145	6240	36	0	0
T146	7044	15	0	0
T147	20158	81	0	0
T148	78985	130	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	3157	0	0
T66	15430	33	0	0
T78	4352	14	0	0
T95	97674	55	0	0
T96	66789	108	0	0
T115	3819	6	0	0
T124	234395	417	0	0
T145	6240	32	0	0
T146	7044	3	0	0
T147	20158	87	0	0
T148	78985	164	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	3601	0	0
T66	15430	42	0	0
T78	4352	13	0	0
T95	97674	163	0	0
T96	66789	132	0	0
T112	61905	105	0	0
T124	234395	380	0	0
T145	6240	3	0	0
T146	7044	10	0	0
T147	20158	45	0	0
T148	78985	89	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	5236	0	0
T16	576720	7	0	0
T18	0	17	0	0
T43	203039	0	0	0
T91	224536	0	0	0
T130	0	14	0	0
T150	0	8	0	0
T151	0	31	0	0
T152	0	26	0	0
T153	0	18	0	0
T154	0	18	0	0
T155	0	15	0	0
T156	0	26	0	0
T157	51450	0	0	0
T158	245988	0	0	0
T159	138684	0	0	0
T160	2945	0	0	0
T161	175419	0	0	0
T162	634515	0	0	0
T163	71417	0	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2881	0	0
T66	15430	29	0	0
T78	4352	13	0	0
T95	97674	82	0	0
T96	66789	85	0	0
T112	61905	51	0	0
T124	234395	340	0	0
T145	6240	22	0	0
T146	7044	29	0	0
T147	20158	58	0	0
T148	78985	143	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2901	0	0
T66	15430	25	0	0
T78	4352	5	0	0
T95	97674	122	0	0
T96	66789	110	0	0
T115	3819	1	0	0
T124	234395	469	0	0
T145	6240	30	0	0
T146	7044	14	0	0
T147	20158	60	0	0
T148	78985	127	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2512	0	0
T66	15430	15	0	0
T78	4352	13	0	0
T95	97674	51	0	0
T96	66789	80	0	0
T112	61905	36	0	0
T124	234395	433	0	0
T145	6240	1	0	0
T146	7044	4	0	0
T147	20158	12	0	0
T148	78985	94	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2762	0	0
T66	15430	25	0	0
T78	4352	15	0	0
T95	97674	82	0	0
T96	66789	83	0	0
T115	3819	4	0	0
T124	234395	420	0	0
T145	6240	17	0	0
T146	7044	14	0	0
T147	20158	75	0	0
T148	78985	173	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2561	0	0
T66	15430	27	0	0
T78	4352	10	0	0
T95	97674	48	0	0
T96	66789	74	0	0
T112	61905	34	0	0
T124	234395	455	0	0
T145	6240	8	0	0
T146	7044	16	0	0
T147	20158	53	0	0
T148	78985	129	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2727	0	0
T66	15430	15	0	0
T78	4352	11	0	0
T95	97674	43	0	0
T96	66789	74	0	0
T115	3819	9	0	0
T124	234395	476	0	0
T145	6240	7	0	0
T146	7044	13	0	0
T147	20158	57	0	0
T148	78985	124	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	3454	0	0
T66	15430	38	0	0
T78	4352	16	0	0
T95	97674	170	0	0
T96	66789	192	0	0
T115	3819	19	0	0
T124	234395	359	0	0
T145	6240	6	0	0
T146	7044	13	0	0
T147	20158	100	0	0
T148	78985	142	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2550	0	0
T66	15430	31	0	0
T78	4352	7	0	0
T95	97674	24	0	0
T96	66789	78	0	0
T115	3819	7	0	0
T124	234395	409	0	0
T145	6240	10	0	0
T146	7044	9	0	0
T147	20158	37	0	0
T148	78985	128	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	3915	0	0
T66	15430	47	0	0
T78	4352	7	0	0
T95	97674	244	0	0
T96	66789	170	0	0
T115	3819	3	0	0
T124	234395	371	0	0
T145	6240	21	0	0
T146	7044	15	0	0
T147	20158	74	0	0
T148	78985	123	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2871	0	0
T66	15430	37	0	0
T78	4352	18	0	0
T95	97674	113	0	0
T96	66789	89	0	0
T115	3819	8	0	0
T124	234395	381	0	0
T145	6240	5	0	0
T146	7044	5	0	0
T147	20158	62	0	0
T148	78985	111	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2695	0	0
T66	15430	33	0	0
T78	4352	18	0	0
T95	97674	67	0	0
T96	66789	70	0	0
T112	61905	44	0	0
T124	234395	397	0	0
T145	6240	17	0	0
T146	7044	30	0	0
T147	20158	71	0	0
T148	78985	116	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2573	0	0
T66	15430	34	0	0
T78	4352	16	0	0
T95	97674	57	0	0
T96	66789	64	0	0
T115	3819	7	0	0
T124	234395	376	0	0
T145	6240	7	0	0
T146	7044	10	0	0
T147	20158	55	0	0
T148	78985	117	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2673	0	0
T66	15430	14	0	0
T78	4352	11	0	0
T95	97674	66	0	0
T96	66789	65	0	0
T115	3819	2	0	0
T124	234395	401	0	0
T145	6240	13	0	0
T146	7044	27	0	0
T147	20158	64	0	0
T148	78985	119	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2723	0	0
T66	15430	32	0	0
T78	4352	13	0	0
T95	97674	70	0	0
T96	66789	86	0	0
T112	61905	35	0	0
T124	234395	447	0	0
T145	6240	4	0	0
T146	7044	28	0	0
T147	20158	32	0	0
T148	78985	101	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2585	0	0
T66	15430	28	0	0
T78	4352	9	0	0
T95	97674	58	0	0
T96	66789	74	0	0
T115	3819	2	0	0
T124	234395	423	0	0
T145	6240	21	0	0
T146	7044	16	0	0
T147	20158	61	0	0
T148	78985	121	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530098809	2565	0	0
T66	15430	39	0	0
T78	4352	14	0	0
T95	97674	46	0	0
T96	66789	68	0	0
T115	3819	7	0	0
T124	234395	375	0	0
T145	6240	11	0	0
T146	7044	19	0	0
T147	20158	69	0	0
T148	78985	130	0	0