Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3218828	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4028965

1

T1

43355

T2

888

T3

2637

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3943373	1			T1	29705		T2	8		T3	8350
values[0x0]	1651470	1			T1	20634		T2	450		T3	1356
values[0x1]	1652950	1			T1	20944		T2	434		T3	1314

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2292739	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4955054

1

T1

51835

T2

889

T3

5319

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26600	1			T1	293		T3	43		T6	8
valid_sources[0x01]	31291	1			T1	284		T2	6		T3	51
valid_sources[0x02]	23581	1			T1	295		T2	2		T3	44
valid_sources[0x03]	25171	1			T1	245		T2	3		T3	76
valid_sources[0x04]	25968	1			T1	285		T2	7		T3	35
valid_sources[0x05]	27964	1			T1	246		T2	1		T3	55
valid_sources[0x06]	26564	1			T1	314		T2	3		T3	27
valid_sources[0x07]	34359	1			T1	325		T2	5		T3	57
valid_sources[0x08]	25283	1			T1	275		T2	4		T3	46
valid_sources[0x09]	26195	1			T1	322		T2	8		T3	40
valid_sources[0x0a]	28830	1			T1	276		T2	10		T3	36
valid_sources[0x0b]	26099	1			T1	227		T2	8		T3	30
valid_sources[0x0c]	27753	1			T1	280		T2	8		T3	41
valid_sources[0x0d]	26569	1			T1	266		T2	5		T3	41
valid_sources[0x0e]	24188	1			T1	251		T2	3		T3	49
valid_sources[0x0f]	25778	1			T1	275		T2	1		T3	34
valid_sources[0x10]	27207	1			T1	277		T2	2		T3	28
valid_sources[0x11]	27770	1			T1	274		T2	2		T3	46
valid_sources[0x12]	30149	1			T1	268		T2	4		T3	42
valid_sources[0x13]	28509	1			T1	322		T2	5		T3	37
valid_sources[0x14]	27481	1			T1	282		T2	4		T3	41
valid_sources[0x15]	30130	1			T1	300		T3	36		T6	7
valid_sources[0x16]	30687	1			T1	277		T2	7		T3	42
valid_sources[0x17]	26234	1			T1	284		T2	2		T3	42
valid_sources[0x18]	33010	1			T1	318		T2	4		T3	51
valid_sources[0x19]	27124	1			T1	268		T2	1		T3	49
valid_sources[0x1a]	25828	1			T1	291		T2	3		T3	35
valid_sources[0x1b]	26174	1			T1	273		T2	3		T3	55
valid_sources[0x1c]	25143	1			T1	279		T2	7		T3	38
valid_sources[0x1d]	29273	1			T1	303		T2	2		T3	54
valid_sources[0x1e]	29686	1			T1	280		T3	34		T4	1
valid_sources[0x1f]	26253	1			T1	289		T2	2		T3	37
valid_sources[0x20]	29389	1			T1	273		T2	2		T3	42
valid_sources[0x21]	25245	1			T1	255		T3	49		T6	3
valid_sources[0x22]	29135	1			T1	269		T2	2		T3	42
valid_sources[0x23]	26934	1			T1	281		T2	2		T3	53
valid_sources[0x24]	37147	1			T1	305		T2	7		T3	40
valid_sources[0x25]	29620	1			T1	296		T2	5		T3	37
valid_sources[0x26]	24802	1			T1	265		T2	8		T3	30
valid_sources[0x27]	27653	1			T1	282		T2	9		T3	46
valid_sources[0x28]	25783	1			T1	272		T2	6		T3	35
valid_sources[0x29]	27661	1			T1	235		T2	3		T3	42
valid_sources[0x2a]	25352	1			T1	292		T2	6		T3	45
valid_sources[0x2b]	25554	1			T1	268		T2	4		T3	47
valid_sources[0x2c]	26002	1			T1	302		T2	2		T3	55
valid_sources[0x2d]	26945	1			T1	333		T2	1		T3	35
valid_sources[0x2e]	27854	1			T1	304		T2	2		T3	50
valid_sources[0x2f]	25458	1			T1	284		T2	3		T3	86
valid_sources[0x30]	24870	1			T1	309		T2	1		T3	57
valid_sources[0x31]	27206	1			T1	309		T2	10		T3	29
valid_sources[0x32]	24787	1			T1	275		T2	3		T3	38
valid_sources[0x33]	26435	1			T1	247		T2	6		T3	54
valid_sources[0x34]	29375	1			T1	270		T2	3		T3	34
valid_sources[0x35]	26514	1			T1	221		T3	40		T4	1
valid_sources[0x36]	27687	1			T1	263		T2	4		T3	33
valid_sources[0x37]	26515	1			T1	289		T2	6		T3	36
valid_sources[0x38]	25977	1			T1	291		T2	4		T3	49
valid_sources[0x39]	44245	1			T1	301		T2	4		T3	39
valid_sources[0x3a]	29610	1			T1	285		T2	3		T3	48
valid_sources[0x3b]	33635	1			T1	302		T2	3		T3	51
valid_sources[0x3c]	28489	1			T1	261		T2	4		T3	29
valid_sources[0x3d]	28373	1			T1	294		T2	2		T3	39
valid_sources[0x3e]	31864	1			T1	307		T2	1		T3	20
valid_sources[0x3f]	27401	1			T1	291		T2	3		T3	30
valid_sources[0x40]	27212	1			T1	278		T2	2		T3	60
valid_sources[0x41]	28015	1			T1	278		T2	1		T3	39
valid_sources[0x42]	27942	1			T1	285		T2	7		T3	31
valid_sources[0x43]	24191	1			T1	236		T2	1		T3	39
valid_sources[0x44]	28094	1			T1	235		T2	10		T3	54
valid_sources[0x45]	27253	1			T1	244		T2	9		T3	52
valid_sources[0x46]	27626	1			T1	290		T2	3		T3	54
valid_sources[0x47]	27756	1			T1	287		T2	1		T3	48
valid_sources[0x48]	25611	1			T1	284		T2	6		T3	33
valid_sources[0x49]	28194	1			T1	308		T2	6		T3	43
valid_sources[0x4a]	27203	1			T1	268		T2	7		T3	40
valid_sources[0x4b]	26660	1			T1	257		T2	2		T3	48
valid_sources[0x4c]	26252	1			T1	340		T2	2		T3	54
valid_sources[0x4d]	27292	1			T1	236		T2	5		T3	50
valid_sources[0x4e]	25843	1			T1	306		T3	39		T6	5
valid_sources[0x4f]	30076	1			T1	288		T2	8		T3	66
valid_sources[0x50]	26709	1			T1	324		T2	4		T3	34
valid_sources[0x51]	24768	1			T1	326		T2	1		T3	55
valid_sources[0x52]	24656	1			T1	261		T2	3		T3	37
valid_sources[0x53]	27991	1			T1	298		T2	6		T3	33
valid_sources[0x54]	30615	1			T1	302		T2	2		T3	45
valid_sources[0x55]	27793	1			T1	278		T2	3		T3	33
valid_sources[0x56]	26435	1			T1	295		T2	1		T3	41
valid_sources[0x57]	27006	1			T1	293		T3	49		T6	8
valid_sources[0x58]	33566	1			T1	317		T2	6		T3	30
valid_sources[0x59]	25566	1			T1	256		T2	2		T3	28
valid_sources[0x5a]	29144	1			T1	266		T2	2		T3	37
valid_sources[0x5b]	27853	1			T1	235		T2	3		T3	33
valid_sources[0x5c]	26468	1			T1	268		T2	2		T3	35
valid_sources[0x5d]	26169	1			T1	270		T2	2		T3	33
valid_sources[0x5e]	27145	1			T1	296		T2	4		T3	41
valid_sources[0x5f]	25115	1			T1	278		T2	5		T3	44
valid_sources[0x60]	26447	1			T1	283		T2	4		T3	40
valid_sources[0x61]	26641	1			T1	306		T2	8		T3	66
valid_sources[0x62]	26708	1			T1	244		T2	2		T3	46
valid_sources[0x63]	26033	1			T1	263		T2	2		T3	47
valid_sources[0x64]	26844	1			T1	279		T2	5		T3	44
valid_sources[0x65]	28357	1			T1	258		T2	2		T3	48
valid_sources[0x66]	27368	1			T1	245		T2	3		T3	37
valid_sources[0x67]	28043	1			T1	289		T2	3		T3	34
valid_sources[0x68]	30952	1			T1	236		T2	5		T3	46
valid_sources[0x69]	26218	1			T1	284		T2	4		T3	38
valid_sources[0x6a]	29747	1			T1	262		T2	4		T3	34
valid_sources[0x6b]	44845	1			T1	233		T2	4		T3	39
valid_sources[0x6c]	25878	1			T1	292		T2	3		T3	52
valid_sources[0x6d]	27514	1			T1	276		T2	5		T3	32
valid_sources[0x6e]	29308	1			T1	289		T2	1		T3	50
valid_sources[0x6f]	27399	1			T1	234		T3	41		T6	9
valid_sources[0x70]	25454	1			T1	269		T2	3		T3	57
valid_sources[0x71]	48763	1			T1	301		T3	38		T6	4
valid_sources[0x72]	29328	1			T1	264		T2	3		T3	60
valid_sources[0x73]	26495	1			T1	246		T3	40		T6	4
valid_sources[0x74]	27340	1			T1	247		T2	4		T3	54
valid_sources[0x75]	28387	1			T1	328		T2	2		T3	29
valid_sources[0x76]	26810	1			T1	288		T2	1		T3	33
valid_sources[0x77]	25983	1			T1	272		T2	3		T3	38
valid_sources[0x78]	28333	1			T1	286		T2	6		T3	39
valid_sources[0x79]	25884	1			T1	263		T2	2		T3	28
valid_sources[0x7a]	27880	1			T1	288		T2	3		T3	33
valid_sources[0x7b]	25910	1			T1	291		T2	7		T3	44
valid_sources[0x7c]	27818	1			T1	305		T2	6		T3	50
valid_sources[0x7d]	31294	1			T1	252		T2	1		T3	41
valid_sources[0x7e]	35308	1			T1	252		T2	6		T3	44
valid_sources[0x7f]	34876	1			T1	323		T2	1		T3	27
valid_sources[0x80]	25721	1			T1	306		T2	6		T3	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1016332

1

T1

5323

T2

6

T3

664

values[0x0]

all_enables

biggest_size

1517327

1

T1

18984

T2

450

T3

1030

values[0x1]

all_enables

biggest_size

1495306

1

T1

19048

T2

432

T3

943