Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3245308

1

T1

27928

T2

4

T3

8383

full_word

4030553

1

T1

43355

T2

888

T3

2637

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7275451	1			T1	71283		T2	892		T3	11020
auto[TlIntgErrCmd]	121	1			T68	2		T69	6		T98	8
auto[TlIntgErrData]	131	1			T68	5		T69	5		T98	8
auto[TlIntgErrBoth]	158	1			T68	3		T69	9		T98	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3948661

1

T1

29705

T2

8

T3

8350

auto[1]

3327200

1

T1

41578

T2

884

T3

2670

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2931743	1			T1	24382		T2	2		T3	7686
auto[TlIntgErrNone]	partial	auto[1]	313188	1			T1	3546		T2	2		T3	697
auto[TlIntgErrNone]	full_word	auto[0]	1016737	1			T1	5323		T2	6		T3	664
auto[TlIntgErrNone]	full_word	auto[1]	3013783	1			T1	38032		T2	882		T3	1973
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T69	3		T98	2		T111	1
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T68	2		T69	3		T98	6
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T111	2		T174	1		T172	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T111	1		T113	1		T174	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T68	4		T69	1		T98	4
auto[TlIntgErrData]	partial	auto[1]	63	1			T68	1		T69	4		T98	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T98	1		T113	1		T175	2
auto[TlIntgErrData]	full_word	auto[1]	2	1			T175	1		T176	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	65	1			T68	2		T69	6		T98	1
auto[TlIntgErrBoth]	partial	auto[1]	82	1			T68	1		T69	3		T98	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T111	1		T172	1		T177	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T98	1		T172	1		T169	1