Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Unreachable
1	1	Covered	T1,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T13
1	0	Covered	T1,T7,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Unreachable
1	1	Covered	T1,T7,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	742930713	596590641	0	0
CheckNGreaterZero_A	2862	2862	0	0
GntImpliesReady_A	742930713	3460306	0	0
GntImpliesValid_A	742930713	3460306	0	0
GrantKnown_A	742930713	596590641	0	0
IdxKnown_A	742930713	596590641	0	0
IndexIsCorrect_A	742930713	3460306	0	0
LockArbDecision_A	742930713	0	0	0
NoReadyValidNoGrant_A	742930713	0	0	0
ReadyAndValidImplyGrant_A	742930713	3460306	0	0
ReqAndReadyImplyGrant_A	742930713	3460306	0	0
ReqImpliesValid_A	742930713	3460306	0	0
ReqStaysHighUntilGranted0_M	742930713	0	0	0
RoundRobin_A	742930713	2	0	954
ValidKnown_A	742930713	596590641	0	0
gen_data_port_assertion.DataFlow_A	742930713	3460306	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742930713	596590641	0	0
T1	912747	911536	0	0
T2	133773	107512	0	0
T3	821259	735978	0	0
T4	1595	1530	0	0
T5	1227	1138	0	0
T6	201870	119841	0	0
T7	1259876	774291	0	0
T8	8578	7703	0	0
T9	436959	309273	0	0
T10	2015	1485	0	0
T11	31674	14870	0	0
T12	131108	65554	0	0
T13	0	371985	0	0
T14	0	6208	0	0
T16	0	24944	0	0
T18	0	139393	0	0
T19	0	21881	0	0
T23	0	376176	0	0
T24	0	34472	0	0
T25	0	2424	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2862	2862	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742930713	3460306	0	0
T1	912747	41990	0	0
T2	133773	832	0	0
T3	821259	4547	0	0
T4	1595	0	0	0
T5	1227	0	0	0
T6	201870	1568	0	0
T7	1259876	21043	0	0
T8	8578	46	0	0
T9	436959	0	0	0
T10	2015	5	0	0
T11	31674	832	0	0
T12	131108	832	0	0
T13	0	14652	0	0
T18	0	266	0	0
T20	0	6387	0	0
T23	0	4601	0	0
T24	0	1718	0	0
T25	0	136	0	0
T34	0	1296	0	0
T43	0	3271	0	0
T49	0	4494	0	0
T50	0	1040	0	0
T51	0	1037	0	0
T52	0	2060	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742930713	3460306	0	0
T1	912747	41990	0	0
T2	133773	832	0	0
T3	821259	4547	0	0
T4	1595	0	0	0
T5	1227	0	0	0
T6	201870	1568	0	0
T7	1259876	21043	0	0
T8	8578	46	0	0
T9	436959	0	0	0
T10	2015	5	0	0
T11	31674	832	0	0
T12	131108	832	0	0
T13	0	14652	0	0
T18	0	266	0	0
T20	0	6387	0	0
T23	0	4601	0	0
T24	0	1718	0	0
T25	0	136	0	0
T34	0	1296	0	0
T43	0	3271	0	0
T49	0	4494	0	0
T50	0	1040	0	0
T51	0	1037	0	0
T52	0	2060	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742930713	596590641	0	0
T1	912747	911536	0	0
T2	133773	107512	0	0
T3	821259	735978	0	0
T4	1595	1530	0	0
T5	1227	1138	0	0
T6	201870	119841	0	0
T7	1259876	774291	0	0
T8	8578	7703	0	0
T9	436959	309273	0	0
T10	2015	1485	0	0
T11	31674	14870	0	0
T12	131108	65554	0	0
T13	0	371985	0	0
T14	0	6208	0	0
T16	0	24944	0	0
T18	0	139393	0	0
T19	0	21881	0	0
T23	0	376176	0	0
T24	0	34472	0	0
T25	0	2424	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742930713	596590641	0	0
T1	912747	911536	0	0
T2	133773	107512	0	0
T3	821259	735978	0	0
T4	1595	1530	0	0
T5	1227	1138	0	0
T6	201870	119841	0	0
T7	1259876	774291	0	0
T8	8578	7703	0	0
T9	436959	309273	0	0
T10	2015	1485	0	0
T11	31674	14870	0	0
T12	131108	65554	0	0
T13	0	371985	0	0
T14	0	6208	0	0
T16	0	24944	0	0
T18	0	139393	0	0
T19	0	21881	0	0
T23	0	376176	0	0
T24	0	34472	0	0
T25	0	2424	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742930713	3460306	0	0
T1	912747	41990	0	0
T2	133773	832	0	0
T3	821259	4547	0	0
T4	1595	0	0	0
T5	1227	0	0	0
T6	201870	1568	0	0
T7	1259876	21043	0	0
T8	8578	46	0	0
T9	436959	0	0	0
T10	2015	5	0	0
T11	31674	832	0	0
T12	131108	832	0	0
T13	0	14652	0	0
T18	0	266	0	0
T20	0	6387	0	0
T23	0	4601	0	0
T24	0	1718	0	0
T25	0	136	0	0
T34	0	1296	0	0
T43	0	3271	0	0
T49	0	4494	0	0
T50	0	1040	0	0
T51	0	1037	0	0
T52	0	2060	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742930713	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742930713	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742930713	3460306	0	0
T1	912747	41990	0	0
T2	133773	832	0	0
T3	821259	4547	0	0
T4	1595	0	0	0
T5	1227	0	0	0
T6	201870	1568	0	0
T7	1259876	21043	0	0
T8	8578	46	0	0
T9	436959	0	0	0
T10	2015	5	0	0
T11	31674	832	0	0
T12	131108	832	0	0
T13	0	14652	0	0
T18	0	266	0	0
T20	0	6387	0	0
T23	0	4601	0	0
T24	0	1718	0	0
T25	0	136	0	0
T34	0	1296	0	0
T43	0	3271	0	0
T49	0	4494	0	0
T50	0	1040	0	0
T51	0	1037	0	0
T52	0	2060	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742930713	3460306	0	0
T1	912747	41990	0	0
T2	133773	832	0	0
T3	821259	4547	0	0
T4	1595	0	0	0
T5	1227	0	0	0
T6	201870	1568	0	0
T7	1259876	21043	0	0
T8	8578	46	0	0
T9	436959	0	0	0
T10	2015	5	0	0
T11	31674	832	0	0
T12	131108	832	0	0
T13	0	14652	0	0
T18	0	266	0	0
T20	0	6387	0	0
T23	0	4601	0	0
T24	0	1718	0	0
T25	0	136	0	0
T34	0	1296	0	0
T43	0	3271	0	0
T49	0	4494	0	0
T50	0	1040	0	0
T51	0	1037	0	0
T52	0	2060	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742930713	3460306	0	0
T1	912747	41990	0	0
T2	133773	832	0	0
T3	821259	4547	0	0
T4	1595	0	0	0
T5	1227	0	0	0
T6	201870	1568	0	0
T7	1259876	21043	0	0
T8	8578	46	0	0
T9	436959	0	0	0
T10	2015	5	0	0
T11	31674	832	0	0
T12	131108	832	0	0
T13	0	14652	0	0
T18	0	266	0	0
T20	0	6387	0	0
T23	0	4601	0	0
T24	0	1718	0	0
T25	0	136	0	0
T34	0	1296	0	0
T43	0	3271	0	0
T49	0	4494	0	0
T50	0	1040	0	0
T51	0	1037	0	0
T52	0	2060	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	742930713	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742930713	2	0	954
T53	571432	1	0	1
T54	0	1	0	0
T55	78924	0	0	1
T56	3071	0	0	1
T57	477991	0	0	1
T58	788209	0	0	1
T59	902547	0	0	1
T60	182153	0	0	1
T61	3808	0	0	1
T62	50516	0	0	1
T63	1214	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742930713	596590641	0	0
T1	912747	911536	0	0
T2	133773	107512	0	0
T3	821259	735978	0	0
T4	1595	1530	0	0
T5	1227	1138	0	0
T6	201870	119841	0	0
T7	1259876	774291	0	0
T8	8578	7703	0	0
T9	436959	309273	0	0
T10	2015	1485	0	0
T11	31674	14870	0	0
T12	131108	65554	0	0
T13	0	371985	0	0
T14	0	6208	0	0
T16	0	24944	0	0
T18	0	139393	0	0
T19	0	21881	0	0
T23	0	376176	0	0
T24	0	34472	0	0
T25	0	2424	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742930713	3460306	0	0
T1	912747	41990	0	0
T2	133773	832	0	0
T3	821259	4547	0	0
T4	1595	0	0	0
T5	1227	0	0	0
T6	201870	1568	0	0
T7	1259876	21043	0	0
T8	8578	46	0	0
T9	436959	0	0	0
T10	2015	5	0	0
T11	31674	832	0	0
T12	131108	832	0	0
T13	0	14652	0	0
T18	0	266	0	0
T20	0	6387	0	0
T23	0	4601	0	0
T24	0	1718	0	0
T25	0	136	0	0
T34	0	1296	0	0
T43	0	3271	0	0
T49	0	4494	0	0
T50	0	1040	0	0
T51	0	1037	0	0
T52	0	2060	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Unreachable
1	1	Covered	T1,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	144935009	27687753	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	144935009	559464	0	0
GntImpliesValid_A	144935009	559464	0	0
GrantKnown_A	144935009	27687753	0	0
IdxKnown_A	144935009	27687753	0	0
IndexIsCorrect_A	144935009	559464	0	0
LockArbDecision_A	144935009	0	0	0
NoReadyValidNoGrant_A	144935009	0	0	0
ReadyAndValidImplyGrant_A	144935009	559464	0	0
ReqAndReadyImplyGrant_A	144935009	559464	0	0
ReqImpliesValid_A	144935009	559464	0	0
ReqStaysHighUntilGranted0_M	144935009	0	0	0
RoundRobin_A	144935009	0	0	0
ValidKnown_A	144935009	27687753	0	0
gen_data_port_assertion.DataFlow_A	144935009	559464	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	27687753	0	0
T1	224167	249192	0	0
T2	26196	0	0	0
T3	80427	75656	0	0
T6	80892	79832	0	0
T7	482058	38560	0	0
T8	824	824	0	0
T9	120290	112944	0	0
T10	336	208	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T23	0	376176	0	0
T24	0	34472	0	0
T25	0	2424	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	559464	0	0
T1	224167	7981	0	0
T2	26196	0	0	0
T3	80427	3077	0	0
T6	80892	1075	0	0
T7	482058	1526	0	0
T8	824	27	0	0
T9	120290	0	0	0
T10	336	3	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T23	0	4601	0	0
T24	0	1718	0	0
T25	0	136	0	0
T49	0	4494	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	559464	0	0
T1	224167	7981	0	0
T2	26196	0	0	0
T3	80427	3077	0	0
T6	80892	1075	0	0
T7	482058	1526	0	0
T8	824	27	0	0
T9	120290	0	0	0
T10	336	3	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T23	0	4601	0	0
T24	0	1718	0	0
T25	0	136	0	0
T49	0	4494	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	27687753	0	0
T1	224167	249192	0	0
T2	26196	0	0	0
T3	80427	75656	0	0
T6	80892	79832	0	0
T7	482058	38560	0	0
T8	824	824	0	0
T9	120290	112944	0	0
T10	336	208	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T23	0	376176	0	0
T24	0	34472	0	0
T25	0	2424	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	27687753	0	0
T1	224167	249192	0	0
T2	26196	0	0	0
T3	80427	75656	0	0
T6	80892	79832	0	0
T7	482058	38560	0	0
T8	824	824	0	0
T9	120290	112944	0	0
T10	336	208	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T23	0	376176	0	0
T24	0	34472	0	0
T25	0	2424	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	559464	0	0
T1	224167	7981	0	0
T2	26196	0	0	0
T3	80427	3077	0	0
T6	80892	1075	0	0
T7	482058	1526	0	0
T8	824	27	0	0
T9	120290	0	0	0
T10	336	3	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T23	0	4601	0	0
T24	0	1718	0	0
T25	0	136	0	0
T49	0	4494	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	559464	0	0
T1	224167	7981	0	0
T2	26196	0	0	0
T3	80427	3077	0	0
T6	80892	1075	0	0
T7	482058	1526	0	0
T8	824	27	0	0
T9	120290	0	0	0
T10	336	3	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T23	0	4601	0	0
T24	0	1718	0	0
T25	0	136	0	0
T49	0	4494	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	559464	0	0
T1	224167	7981	0	0
T2	26196	0	0	0
T3	80427	3077	0	0
T6	80892	1075	0	0
T7	482058	1526	0	0
T8	824	27	0	0
T9	120290	0	0	0
T10	336	3	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T23	0	4601	0	0
T24	0	1718	0	0
T25	0	136	0	0
T49	0	4494	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	559464	0	0
T1	224167	7981	0	0
T2	26196	0	0	0
T3	80427	3077	0	0
T6	80892	1075	0	0
T7	482058	1526	0	0
T8	824	27	0	0
T9	120290	0	0	0
T10	336	3	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T23	0	4601	0	0
T24	0	1718	0	0
T25	0	136	0	0
T49	0	4494	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	27687753	0	0
T1	224167	249192	0	0
T2	26196	0	0	0
T3	80427	75656	0	0
T6	80892	79832	0	0
T7	482058	38560	0	0
T8	824	824	0	0
T9	120290	112944	0	0
T10	336	208	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T23	0	376176	0	0
T24	0	34472	0	0
T25	0	2424	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	559464	0	0
T1	224167	7981	0	0
T2	26196	0	0	0
T3	80427	3077	0	0
T6	80892	1075	0	0
T7	482058	1526	0	0
T8	824	27	0	0
T9	120290	0	0	0
T10	336	3	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T23	0	4601	0	0
T24	0	1718	0	0
T25	0	136	0	0
T49	0	4494	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T13
1	0	Covered	T1,T7,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Unreachable
1	1	Covered	T1,T7,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T7,T13
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	144935009	115929561	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	144935009	711955	0	0
GntImpliesValid_A	144935009	711955	0	0
GrantKnown_A	144935009	115929561	0	0
IdxKnown_A	144935009	115929561	0	0
IndexIsCorrect_A	144935009	711955	0	0
LockArbDecision_A	144935009	0	0	0
NoReadyValidNoGrant_A	144935009	0	0	0
ReadyAndValidImplyGrant_A	144935009	711955	0	0
ReqAndReadyImplyGrant_A	144935009	711955	0	0
ReqImpliesValid_A	144935009	711955	0	0
ReqStaysHighUntilGranted0_M	144935009	0	0	0
RoundRobin_A	144935009	0	0	0
ValidKnown_A	144935009	115929561	0	0
gen_data_port_assertion.DataFlow_A	144935009	711955	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	115929561	0	0
T1	224167	197956	0	0
T2	26196	26196	0	0
T3	80427	0	0	0
T6	80892	0	0	0
T7	482058	439979	0	0
T8	824	0	0	0
T9	120290	0	0	0
T10	336	0	0	0
T11	15837	14870	0	0
T12	65554	65554	0	0
T13	0	371985	0	0
T14	0	6208	0	0
T16	0	24944	0	0
T18	0	139393	0	0
T19	0	21881	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	711955	0	0
T1	224167	4608	0	0
T2	26196	0	0	0
T3	80427	0	0	0
T6	80892	0	0	0
T7	482058	7906	0	0
T8	824	0	0	0
T9	120290	0	0	0
T10	336	0	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T13	0	5033	0	0
T18	0	266	0	0
T20	0	6387	0	0
T34	0	1296	0	0
T43	0	3271	0	0
T50	0	1040	0	0
T51	0	1037	0	0
T52	0	2060	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	711955	0	0
T1	224167	4608	0	0
T2	26196	0	0	0
T3	80427	0	0	0
T6	80892	0	0	0
T7	482058	7906	0	0
T8	824	0	0	0
T9	120290	0	0	0
T10	336	0	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T13	0	5033	0	0
T18	0	266	0	0
T20	0	6387	0	0
T34	0	1296	0	0
T43	0	3271	0	0
T50	0	1040	0	0
T51	0	1037	0	0
T52	0	2060	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	115929561	0	0
T1	224167	197956	0	0
T2	26196	26196	0	0
T3	80427	0	0	0
T6	80892	0	0	0
T7	482058	439979	0	0
T8	824	0	0	0
T9	120290	0	0	0
T10	336	0	0	0
T11	15837	14870	0	0
T12	65554	65554	0	0
T13	0	371985	0	0
T14	0	6208	0	0
T16	0	24944	0	0
T18	0	139393	0	0
T19	0	21881	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	115929561	0	0
T1	224167	197956	0	0
T2	26196	26196	0	0
T3	80427	0	0	0
T6	80892	0	0	0
T7	482058	439979	0	0
T8	824	0	0	0
T9	120290	0	0	0
T10	336	0	0	0
T11	15837	14870	0	0
T12	65554	65554	0	0
T13	0	371985	0	0
T14	0	6208	0	0
T16	0	24944	0	0
T18	0	139393	0	0
T19	0	21881	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	711955	0	0
T1	224167	4608	0	0
T2	26196	0	0	0
T3	80427	0	0	0
T6	80892	0	0	0
T7	482058	7906	0	0
T8	824	0	0	0
T9	120290	0	0	0
T10	336	0	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T13	0	5033	0	0
T18	0	266	0	0
T20	0	6387	0	0
T34	0	1296	0	0
T43	0	3271	0	0
T50	0	1040	0	0
T51	0	1037	0	0
T52	0	2060	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	711955	0	0
T1	224167	4608	0	0
T2	26196	0	0	0
T3	80427	0	0	0
T6	80892	0	0	0
T7	482058	7906	0	0
T8	824	0	0	0
T9	120290	0	0	0
T10	336	0	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T13	0	5033	0	0
T18	0	266	0	0
T20	0	6387	0	0
T34	0	1296	0	0
T43	0	3271	0	0
T50	0	1040	0	0
T51	0	1037	0	0
T52	0	2060	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	711955	0	0
T1	224167	4608	0	0
T2	26196	0	0	0
T3	80427	0	0	0
T6	80892	0	0	0
T7	482058	7906	0	0
T8	824	0	0	0
T9	120290	0	0	0
T10	336	0	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T13	0	5033	0	0
T18	0	266	0	0
T20	0	6387	0	0
T34	0	1296	0	0
T43	0	3271	0	0
T50	0	1040	0	0
T51	0	1037	0	0
T52	0	2060	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	711955	0	0
T1	224167	4608	0	0
T2	26196	0	0	0
T3	80427	0	0	0
T6	80892	0	0	0
T7	482058	7906	0	0
T8	824	0	0	0
T9	120290	0	0	0
T10	336	0	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T13	0	5033	0	0
T18	0	266	0	0
T20	0	6387	0	0
T34	0	1296	0	0
T43	0	3271	0	0
T50	0	1040	0	0
T51	0	1037	0	0
T52	0	2060	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	115929561	0	0
T1	224167	197956	0	0
T2	26196	26196	0	0
T3	80427	0	0	0
T6	80892	0	0	0
T7	482058	439979	0	0
T8	824	0	0	0
T9	120290	0	0	0
T10	336	0	0	0
T11	15837	14870	0	0
T12	65554	65554	0	0
T13	0	371985	0	0
T14	0	6208	0	0
T16	0	24944	0	0
T18	0	139393	0	0
T19	0	21881	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144935009	711955	0	0
T1	224167	4608	0	0
T2	26196	0	0	0
T3	80427	0	0	0
T6	80892	0	0	0
T7	482058	7906	0	0
T8	824	0	0	0
T9	120290	0	0	0
T10	336	0	0	0
T11	15837	0	0	0
T12	65554	0	0	0
T13	0	5033	0	0
T18	0	266	0	0
T20	0	6387	0	0
T34	0	1296	0	0
T43	0	3271	0	0
T50	0	1040	0	0
T51	0	1037	0	0
T52	0	2060	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453060695	452973327	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	453060695	2188887	0	0
GntImpliesValid_A	453060695	2188887	0	0
GrantKnown_A	453060695	452973327	0	0
IdxKnown_A	453060695	452973327	0	0
IndexIsCorrect_A	453060695	2188887	0	0
LockArbDecision_A	453060695	0	0	0
NoReadyValidNoGrant_A	453060695	0	0	0
ReadyAndValidImplyGrant_A	453060695	2188887	0	0
ReqAndReadyImplyGrant_A	453060695	2188887	0	0
ReqImpliesValid_A	453060695	2188887	0	0
ReqStaysHighUntilGranted0_M	453060695	0	0	0
RoundRobin_A	453060695	2	0	954
ValidKnown_A	453060695	452973327	0	0
gen_data_port_assertion.DataFlow_A	453060695	2188887	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453060695	452973327	0	0
T1	464413	464388	0	0
T2	81381	81316	0	0
T3	660405	660322	0	0
T4	1595	1530	0	0
T5	1227	1138	0	0
T6	40086	40009	0	0
T7	295760	295752	0	0
T8	6930	6879	0	0
T9	196379	196329	0	0
T10	1343	1277	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453060695	2188887	0	0
T1	464413	29401	0	0
T2	81381	832	0	0
T3	660405	1470	0	0
T4	1595	0	0	0
T5	1227	0	0	0
T6	40086	493	0	0
T7	295760	11611	0	0
T8	6930	19	0	0
T9	196379	0	0	0
T10	1343	2	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	9619	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453060695	2188887	0	0
T1	464413	29401	0	0
T2	81381	832	0	0
T3	660405	1470	0	0
T4	1595	0	0	0
T5	1227	0	0	0
T6	40086	493	0	0
T7	295760	11611	0	0
T8	6930	19	0	0
T9	196379	0	0	0
T10	1343	2	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	9619	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453060695	452973327	0	0
T1	464413	464388	0	0
T2	81381	81316	0	0
T3	660405	660322	0	0
T4	1595	1530	0	0
T5	1227	1138	0	0
T6	40086	40009	0	0
T7	295760	295752	0	0
T8	6930	6879	0	0
T9	196379	196329	0	0
T10	1343	1277	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453060695	452973327	0	0
T1	464413	464388	0	0
T2	81381	81316	0	0
T3	660405	660322	0	0
T4	1595	1530	0	0
T5	1227	1138	0	0
T6	40086	40009	0	0
T7	295760	295752	0	0
T8	6930	6879	0	0
T9	196379	196329	0	0
T10	1343	1277	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453060695	2188887	0	0
T1	464413	29401	0	0
T2	81381	832	0	0
T3	660405	1470	0	0
T4	1595	0	0	0
T5	1227	0	0	0
T6	40086	493	0	0
T7	295760	11611	0	0
T8	6930	19	0	0
T9	196379	0	0	0
T10	1343	2	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	9619	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453060695	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453060695	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453060695	2188887	0	0
T1	464413	29401	0	0
T2	81381	832	0	0
T3	660405	1470	0	0
T4	1595	0	0	0
T5	1227	0	0	0
T6	40086	493	0	0
T7	295760	11611	0	0
T8	6930	19	0	0
T9	196379	0	0	0
T10	1343	2	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	9619	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453060695	2188887	0	0
T1	464413	29401	0	0
T2	81381	832	0	0
T3	660405	1470	0	0
T4	1595	0	0	0
T5	1227	0	0	0
T6	40086	493	0	0
T7	295760	11611	0	0
T8	6930	19	0	0
T9	196379	0	0	0
T10	1343	2	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	9619	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453060695	2188887	0	0
T1	464413	29401	0	0
T2	81381	832	0	0
T3	660405	1470	0	0
T4	1595	0	0	0
T5	1227	0	0	0
T6	40086	493	0	0
T7	295760	11611	0	0
T8	6930	19	0	0
T9	196379	0	0	0
T10	1343	2	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	9619	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453060695	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453060695	2	0	954
T53	571432	1	0	1
T54	0	1	0	0
T55	78924	0	0	1
T56	3071	0	0	1
T57	477991	0	0	1
T58	788209	0	0	1
T59	902547	0	0	1
T60	182153	0	0	1
T61	3808	0	0	1
T62	50516	0	0	1
T63	1214	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453060695	452973327	0	0
T1	464413	464388	0	0
T2	81381	81316	0	0
T3	660405	660322	0	0
T4	1595	1530	0	0
T5	1227	1138	0	0
T6	40086	40009	0	0
T7	295760	295752	0	0
T8	6930	6879	0	0
T9	196379	196329	0	0
T10	1343	1277	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453060695	2188887	0	0
T1	464413	29401	0	0
T2	81381	832	0	0
T3	660405	1470	0	0
T4	1595	0	0	0
T5	1227	0	0	0
T6	40086	493	0	0
T7	295760	11611	0	0
T8	6930	19	0	0
T9	196379	0	0	0
T10	1343	2	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	9619	0	0