Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
3643 |
0 |
0 |
T68 |
36765 |
1 |
0 |
0 |
T69 |
66752 |
4 |
0 |
0 |
T70 |
3634 |
90 |
0 |
0 |
T96 |
8754 |
5 |
0 |
0 |
T97 |
2146 |
6 |
0 |
0 |
T98 |
52864 |
3 |
0 |
0 |
T99 |
3330 |
72 |
0 |
0 |
T100 |
4253 |
147 |
0 |
0 |
T111 |
29201 |
4 |
0 |
0 |
T112 |
3467 |
9 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1707 |
0 |
0 |
T68 |
36765 |
28 |
0 |
0 |
T69 |
66752 |
87 |
0 |
0 |
T114 |
5815 |
12 |
0 |
0 |
T115 |
9834 |
21 |
0 |
0 |
T122 |
6673 |
9 |
0 |
0 |
T123 |
11672 |
10 |
0 |
0 |
T134 |
8653 |
7 |
0 |
0 |
T143 |
37200 |
145 |
0 |
0 |
T144 |
181316 |
482 |
0 |
0 |
T145 |
90337 |
184 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1691 |
0 |
0 |
T68 |
36765 |
33 |
0 |
0 |
T69 |
66752 |
81 |
0 |
0 |
T114 |
5815 |
2 |
0 |
0 |
T115 |
9834 |
18 |
0 |
0 |
T122 |
6673 |
5 |
0 |
0 |
T123 |
11672 |
17 |
0 |
0 |
T134 |
8653 |
3 |
0 |
0 |
T143 |
37200 |
148 |
0 |
0 |
T144 |
181316 |
495 |
0 |
0 |
T145 |
90337 |
243 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
2138 |
0 |
0 |
T68 |
36765 |
55 |
0 |
0 |
T69 |
66752 |
155 |
0 |
0 |
T114 |
5815 |
12 |
0 |
0 |
T115 |
9834 |
34 |
0 |
0 |
T122 |
6673 |
4 |
0 |
0 |
T123 |
11672 |
28 |
0 |
0 |
T134 |
8653 |
8 |
0 |
0 |
T143 |
37200 |
195 |
0 |
0 |
T144 |
181316 |
439 |
0 |
0 |
T145 |
90337 |
217 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
9847 |
0 |
0 |
T68 |
36765 |
443 |
0 |
0 |
T69 |
66752 |
1204 |
0 |
0 |
T114 |
5815 |
5 |
0 |
0 |
T115 |
9834 |
135 |
0 |
0 |
T122 |
6673 |
8 |
0 |
0 |
T123 |
11672 |
345 |
0 |
0 |
T134 |
8653 |
133 |
0 |
0 |
T143 |
37200 |
158 |
0 |
0 |
T144 |
181316 |
417 |
0 |
0 |
T145 |
90337 |
216 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
10192 |
0 |
0 |
T68 |
36765 |
831 |
0 |
0 |
T69 |
66752 |
1143 |
0 |
0 |
T114 |
5815 |
99 |
0 |
0 |
T115 |
9834 |
15 |
0 |
0 |
T122 |
6673 |
121 |
0 |
0 |
T123 |
11672 |
214 |
0 |
0 |
T134 |
8653 |
98 |
0 |
0 |
T143 |
37200 |
129 |
0 |
0 |
T144 |
181316 |
440 |
0 |
0 |
T145 |
90337 |
264 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
10537 |
0 |
0 |
T68 |
36765 |
818 |
0 |
0 |
T69 |
66752 |
996 |
0 |
0 |
T114 |
5815 |
5 |
0 |
0 |
T115 |
9834 |
20 |
0 |
0 |
T122 |
6673 |
4 |
0 |
0 |
T123 |
11672 |
126 |
0 |
0 |
T134 |
8653 |
240 |
0 |
0 |
T143 |
37200 |
148 |
0 |
0 |
T144 |
181316 |
440 |
0 |
0 |
T145 |
90337 |
234 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
9137 |
0 |
0 |
T68 |
36765 |
745 |
0 |
0 |
T69 |
66752 |
838 |
0 |
0 |
T114 |
5815 |
95 |
0 |
0 |
T115 |
9834 |
14 |
0 |
0 |
T122 |
6673 |
117 |
0 |
0 |
T123 |
11672 |
129 |
0 |
0 |
T134 |
8653 |
209 |
0 |
0 |
T143 |
37200 |
148 |
0 |
0 |
T144 |
181316 |
446 |
0 |
0 |
T145 |
90337 |
214 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
10082 |
0 |
0 |
T68 |
36765 |
790 |
0 |
0 |
T69 |
66752 |
1302 |
0 |
0 |
T114 |
5815 |
3 |
0 |
0 |
T115 |
9834 |
130 |
0 |
0 |
T122 |
6673 |
213 |
0 |
0 |
T123 |
11672 |
105 |
0 |
0 |
T134 |
8653 |
117 |
0 |
0 |
T143 |
37200 |
114 |
0 |
0 |
T144 |
181316 |
465 |
0 |
0 |
T145 |
90337 |
212 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
12096 |
0 |
0 |
T68 |
36765 |
575 |
0 |
0 |
T69 |
66752 |
1343 |
0 |
0 |
T114 |
5815 |
5 |
0 |
0 |
T115 |
9834 |
127 |
0 |
0 |
T122 |
6673 |
144 |
0 |
0 |
T123 |
11672 |
270 |
0 |
0 |
T134 |
8653 |
120 |
0 |
0 |
T143 |
37200 |
193 |
0 |
0 |
T144 |
181316 |
436 |
0 |
0 |
T145 |
90337 |
223 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
12672 |
0 |
0 |
T68 |
36765 |
790 |
0 |
0 |
T69 |
66752 |
1921 |
0 |
0 |
T114 |
5815 |
102 |
0 |
0 |
T115 |
9834 |
257 |
0 |
0 |
T122 |
6673 |
203 |
0 |
0 |
T123 |
11672 |
327 |
0 |
0 |
T134 |
8653 |
119 |
0 |
0 |
T143 |
37200 |
122 |
0 |
0 |
T144 |
181316 |
487 |
0 |
0 |
T145 |
90337 |
212 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
9803 |
0 |
0 |
T68 |
36765 |
622 |
0 |
0 |
T69 |
66752 |
1195 |
0 |
0 |
T114 |
5815 |
127 |
0 |
0 |
T115 |
9834 |
18 |
0 |
0 |
T122 |
6673 |
121 |
0 |
0 |
T123 |
11672 |
264 |
0 |
0 |
T134 |
8653 |
6 |
0 |
0 |
T143 |
37200 |
142 |
0 |
0 |
T144 |
181316 |
409 |
0 |
0 |
T145 |
90337 |
233 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5211 |
0 |
0 |
T68 |
36765 |
141 |
0 |
0 |
T69 |
66752 |
540 |
0 |
0 |
T114 |
5815 |
2 |
0 |
0 |
T115 |
9834 |
70 |
0 |
0 |
T122 |
6673 |
37 |
0 |
0 |
T123 |
11672 |
62 |
0 |
0 |
T134 |
8653 |
53 |
0 |
0 |
T143 |
37200 |
147 |
0 |
0 |
T144 |
181316 |
385 |
0 |
0 |
T145 |
90337 |
230 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
4916 |
0 |
0 |
T68 |
36765 |
153 |
0 |
0 |
T69 |
66752 |
651 |
0 |
0 |
T114 |
5815 |
1 |
0 |
0 |
T115 |
9834 |
85 |
0 |
0 |
T122 |
6673 |
51 |
0 |
0 |
T123 |
11672 |
129 |
0 |
0 |
T134 |
8653 |
100 |
0 |
0 |
T143 |
37200 |
165 |
0 |
0 |
T144 |
181316 |
461 |
0 |
0 |
T145 |
90337 |
208 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5690 |
0 |
0 |
T68 |
36765 |
337 |
0 |
0 |
T69 |
66752 |
660 |
0 |
0 |
T114 |
5815 |
59 |
0 |
0 |
T115 |
9834 |
13 |
0 |
0 |
T122 |
6673 |
60 |
0 |
0 |
T123 |
11672 |
81 |
0 |
0 |
T134 |
8653 |
6 |
0 |
0 |
T143 |
37200 |
160 |
0 |
0 |
T144 |
181316 |
478 |
0 |
0 |
T145 |
90337 |
215 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5412 |
0 |
0 |
T68 |
36765 |
348 |
0 |
0 |
T69 |
66752 |
663 |
0 |
0 |
T114 |
5815 |
10 |
0 |
0 |
T115 |
9834 |
21 |
0 |
0 |
T123 |
11672 |
108 |
0 |
0 |
T125 |
4046 |
44 |
0 |
0 |
T134 |
8653 |
48 |
0 |
0 |
T143 |
37200 |
108 |
0 |
0 |
T144 |
181316 |
400 |
0 |
0 |
T145 |
90337 |
235 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5451 |
0 |
0 |
T68 |
36765 |
299 |
0 |
0 |
T69 |
66752 |
429 |
0 |
0 |
T114 |
5815 |
47 |
0 |
0 |
T115 |
9834 |
21 |
0 |
0 |
T122 |
6673 |
38 |
0 |
0 |
T123 |
11672 |
132 |
0 |
0 |
T134 |
8653 |
107 |
0 |
0 |
T143 |
37200 |
176 |
0 |
0 |
T144 |
181316 |
462 |
0 |
0 |
T145 |
90337 |
190 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
4837 |
0 |
0 |
T68 |
36765 |
188 |
0 |
0 |
T69 |
66752 |
560 |
0 |
0 |
T114 |
5815 |
11 |
0 |
0 |
T115 |
9834 |
117 |
0 |
0 |
T122 |
6673 |
1 |
0 |
0 |
T123 |
11672 |
123 |
0 |
0 |
T134 |
8653 |
44 |
0 |
0 |
T143 |
37200 |
121 |
0 |
0 |
T144 |
181316 |
512 |
0 |
0 |
T145 |
90337 |
207 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5496 |
0 |
0 |
T68 |
36765 |
302 |
0 |
0 |
T69 |
66752 |
666 |
0 |
0 |
T114 |
5815 |
55 |
0 |
0 |
T115 |
9834 |
51 |
0 |
0 |
T122 |
6673 |
60 |
0 |
0 |
T123 |
11672 |
36 |
0 |
0 |
T134 |
8653 |
6 |
0 |
0 |
T143 |
37200 |
138 |
0 |
0 |
T144 |
181316 |
440 |
0 |
0 |
T145 |
90337 |
211 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5161 |
0 |
0 |
T68 |
36765 |
238 |
0 |
0 |
T69 |
66752 |
639 |
0 |
0 |
T114 |
5815 |
49 |
0 |
0 |
T115 |
9834 |
114 |
0 |
0 |
T122 |
6673 |
7 |
0 |
0 |
T123 |
11672 |
97 |
0 |
0 |
T134 |
8653 |
55 |
0 |
0 |
T143 |
37200 |
165 |
0 |
0 |
T144 |
181316 |
448 |
0 |
0 |
T145 |
90337 |
221 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5420 |
0 |
0 |
T68 |
36765 |
219 |
0 |
0 |
T69 |
66752 |
485 |
0 |
0 |
T114 |
5815 |
5 |
0 |
0 |
T115 |
9834 |
73 |
0 |
0 |
T122 |
6673 |
5 |
0 |
0 |
T123 |
11672 |
53 |
0 |
0 |
T134 |
8653 |
55 |
0 |
0 |
T143 |
37200 |
130 |
0 |
0 |
T144 |
181316 |
497 |
0 |
0 |
T145 |
90337 |
259 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5160 |
0 |
0 |
T68 |
36765 |
170 |
0 |
0 |
T69 |
66752 |
603 |
0 |
0 |
T114 |
5815 |
37 |
0 |
0 |
T115 |
9834 |
57 |
0 |
0 |
T122 |
6673 |
5 |
0 |
0 |
T123 |
11672 |
145 |
0 |
0 |
T134 |
8653 |
6 |
0 |
0 |
T143 |
37200 |
157 |
0 |
0 |
T144 |
181316 |
434 |
0 |
0 |
T145 |
90337 |
205 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5027 |
0 |
0 |
T68 |
36765 |
283 |
0 |
0 |
T69 |
66752 |
407 |
0 |
0 |
T114 |
5815 |
48 |
0 |
0 |
T115 |
9834 |
63 |
0 |
0 |
T122 |
6673 |
66 |
0 |
0 |
T123 |
11672 |
113 |
0 |
0 |
T134 |
8653 |
49 |
0 |
0 |
T143 |
37200 |
154 |
0 |
0 |
T144 |
181316 |
483 |
0 |
0 |
T145 |
90337 |
212 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5107 |
0 |
0 |
T68 |
36765 |
167 |
0 |
0 |
T69 |
66752 |
482 |
0 |
0 |
T114 |
5815 |
46 |
0 |
0 |
T115 |
9834 |
44 |
0 |
0 |
T122 |
6673 |
47 |
0 |
0 |
T123 |
11672 |
97 |
0 |
0 |
T134 |
8653 |
100 |
0 |
0 |
T143 |
37200 |
100 |
0 |
0 |
T144 |
181316 |
499 |
0 |
0 |
T145 |
90337 |
225 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5387 |
0 |
0 |
T68 |
36765 |
246 |
0 |
0 |
T69 |
66752 |
531 |
0 |
0 |
T114 |
5815 |
7 |
0 |
0 |
T115 |
9834 |
41 |
0 |
0 |
T122 |
6673 |
9 |
0 |
0 |
T123 |
11672 |
55 |
0 |
0 |
T134 |
8653 |
2 |
0 |
0 |
T143 |
37200 |
135 |
0 |
0 |
T144 |
181316 |
465 |
0 |
0 |
T145 |
90337 |
227 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5383 |
0 |
0 |
T68 |
36765 |
305 |
0 |
0 |
T69 |
66752 |
497 |
0 |
0 |
T114 |
5815 |
12 |
0 |
0 |
T115 |
9834 |
127 |
0 |
0 |
T122 |
6673 |
6 |
0 |
0 |
T123 |
11672 |
111 |
0 |
0 |
T134 |
8653 |
55 |
0 |
0 |
T143 |
37200 |
159 |
0 |
0 |
T144 |
181316 |
437 |
0 |
0 |
T145 |
90337 |
226 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5060 |
0 |
0 |
T68 |
36765 |
340 |
0 |
0 |
T69 |
66752 |
529 |
0 |
0 |
T114 |
5815 |
54 |
0 |
0 |
T115 |
9834 |
91 |
0 |
0 |
T122 |
6673 |
9 |
0 |
0 |
T123 |
11672 |
128 |
0 |
0 |
T134 |
8653 |
93 |
0 |
0 |
T143 |
37200 |
157 |
0 |
0 |
T144 |
181316 |
443 |
0 |
0 |
T145 |
90337 |
225 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5240 |
0 |
0 |
T68 |
36765 |
318 |
0 |
0 |
T69 |
66752 |
706 |
0 |
0 |
T114 |
5815 |
6 |
0 |
0 |
T115 |
9834 |
16 |
0 |
0 |
T122 |
6673 |
50 |
0 |
0 |
T123 |
11672 |
70 |
0 |
0 |
T134 |
8653 |
113 |
0 |
0 |
T143 |
37200 |
180 |
0 |
0 |
T144 |
181316 |
446 |
0 |
0 |
T145 |
90337 |
202 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5072 |
0 |
0 |
T68 |
36765 |
200 |
0 |
0 |
T69 |
66752 |
641 |
0 |
0 |
T114 |
5815 |
12 |
0 |
0 |
T115 |
9834 |
69 |
0 |
0 |
T122 |
6673 |
3 |
0 |
0 |
T123 |
11672 |
88 |
0 |
0 |
T134 |
8653 |
110 |
0 |
0 |
T143 |
37200 |
135 |
0 |
0 |
T144 |
181316 |
430 |
0 |
0 |
T145 |
90337 |
225 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5088 |
0 |
0 |
T68 |
36765 |
201 |
0 |
0 |
T69 |
66752 |
320 |
0 |
0 |
T114 |
5815 |
36 |
0 |
0 |
T115 |
9834 |
62 |
0 |
0 |
T122 |
6673 |
10 |
0 |
0 |
T123 |
11672 |
8 |
0 |
0 |
T134 |
8653 |
123 |
0 |
0 |
T143 |
37200 |
145 |
0 |
0 |
T144 |
181316 |
467 |
0 |
0 |
T145 |
90337 |
256 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5169 |
0 |
0 |
T68 |
36765 |
258 |
0 |
0 |
T69 |
66752 |
678 |
0 |
0 |
T114 |
5815 |
41 |
0 |
0 |
T115 |
9834 |
8 |
0 |
0 |
T122 |
6673 |
3 |
0 |
0 |
T123 |
11672 |
66 |
0 |
0 |
T134 |
8653 |
64 |
0 |
0 |
T143 |
37200 |
150 |
0 |
0 |
T144 |
181316 |
438 |
0 |
0 |
T145 |
90337 |
235 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5878 |
0 |
0 |
T68 |
36765 |
259 |
0 |
0 |
T69 |
66752 |
669 |
0 |
0 |
T114 |
5815 |
52 |
0 |
0 |
T115 |
9834 |
68 |
0 |
0 |
T122 |
6673 |
64 |
0 |
0 |
T123 |
11672 |
73 |
0 |
0 |
T134 |
8653 |
9 |
0 |
0 |
T143 |
37200 |
155 |
0 |
0 |
T144 |
181316 |
476 |
0 |
0 |
T145 |
90337 |
221 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5652 |
0 |
0 |
T68 |
36765 |
248 |
0 |
0 |
T69 |
66752 |
623 |
0 |
0 |
T114 |
5815 |
6 |
0 |
0 |
T115 |
9834 |
14 |
0 |
0 |
T122 |
6673 |
3 |
0 |
0 |
T123 |
11672 |
174 |
0 |
0 |
T134 |
8653 |
64 |
0 |
0 |
T143 |
37200 |
164 |
0 |
0 |
T144 |
181316 |
472 |
0 |
0 |
T145 |
90337 |
241 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
5216 |
0 |
0 |
T68 |
36765 |
291 |
0 |
0 |
T69 |
66752 |
486 |
0 |
0 |
T114 |
5815 |
43 |
0 |
0 |
T115 |
9834 |
103 |
0 |
0 |
T122 |
6673 |
97 |
0 |
0 |
T123 |
11672 |
160 |
0 |
0 |
T134 |
8653 |
50 |
0 |
0 |
T143 |
37200 |
145 |
0 |
0 |
T144 |
181316 |
410 |
0 |
0 |
T145 |
90337 |
214 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
4440 |
0 |
0 |
T68 |
36765 |
242 |
0 |
0 |
T69 |
66752 |
541 |
0 |
0 |
T114 |
5815 |
8 |
0 |
0 |
T115 |
9834 |
8 |
0 |
0 |
T122 |
6673 |
65 |
0 |
0 |
T123 |
11672 |
65 |
0 |
0 |
T134 |
8653 |
49 |
0 |
0 |
T143 |
37200 |
146 |
0 |
0 |
T144 |
181316 |
429 |
0 |
0 |
T145 |
90337 |
222 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
4646 |
0 |
0 |
T68 |
36765 |
199 |
0 |
0 |
T69 |
66752 |
586 |
0 |
0 |
T114 |
5815 |
44 |
0 |
0 |
T115 |
9834 |
19 |
0 |
0 |
T122 |
6673 |
48 |
0 |
0 |
T123 |
11672 |
56 |
0 |
0 |
T134 |
8653 |
70 |
0 |
0 |
T143 |
37200 |
137 |
0 |
0 |
T144 |
181316 |
443 |
0 |
0 |
T145 |
90337 |
226 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1916 |
0 |
0 |
T68 |
36765 |
66 |
0 |
0 |
T69 |
66752 |
122 |
0 |
0 |
T114 |
5815 |
7 |
0 |
0 |
T115 |
9834 |
15 |
0 |
0 |
T122 |
6673 |
15 |
0 |
0 |
T123 |
11672 |
10 |
0 |
0 |
T134 |
8653 |
12 |
0 |
0 |
T143 |
37200 |
143 |
0 |
0 |
T144 |
181316 |
468 |
0 |
0 |
T145 |
90337 |
217 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
2115 |
0 |
0 |
T68 |
36765 |
58 |
0 |
0 |
T69 |
66752 |
136 |
0 |
0 |
T114 |
5815 |
15 |
0 |
0 |
T115 |
9834 |
9 |
0 |
0 |
T122 |
6673 |
12 |
0 |
0 |
T123 |
11672 |
20 |
0 |
0 |
T134 |
8653 |
12 |
0 |
0 |
T143 |
37200 |
115 |
0 |
0 |
T144 |
181316 |
502 |
0 |
0 |
T145 |
90337 |
246 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1961 |
0 |
0 |
T68 |
36765 |
55 |
0 |
0 |
T69 |
66752 |
115 |
0 |
0 |
T114 |
5815 |
11 |
0 |
0 |
T115 |
9834 |
17 |
0 |
0 |
T122 |
6673 |
16 |
0 |
0 |
T123 |
11672 |
17 |
0 |
0 |
T134 |
8653 |
9 |
0 |
0 |
T143 |
37200 |
154 |
0 |
0 |
T144 |
181316 |
443 |
0 |
0 |
T145 |
90337 |
204 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
2015 |
0 |
0 |
T68 |
36765 |
64 |
0 |
0 |
T69 |
66752 |
129 |
0 |
0 |
T114 |
5815 |
3 |
0 |
0 |
T115 |
9834 |
30 |
0 |
0 |
T122 |
6673 |
24 |
0 |
0 |
T123 |
11672 |
14 |
0 |
0 |
T134 |
8653 |
11 |
0 |
0 |
T143 |
37200 |
131 |
0 |
0 |
T144 |
181316 |
458 |
0 |
0 |
T145 |
90337 |
228 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
2449 |
0 |
0 |
T68 |
36765 |
78 |
0 |
0 |
T69 |
66752 |
192 |
0 |
0 |
T114 |
5815 |
1 |
0 |
0 |
T115 |
9834 |
13 |
0 |
0 |
T122 |
6673 |
27 |
0 |
0 |
T123 |
11672 |
24 |
0 |
0 |
T134 |
8653 |
1 |
0 |
0 |
T143 |
37200 |
171 |
0 |
0 |
T144 |
181316 |
454 |
0 |
0 |
T145 |
90337 |
253 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
4530 |
0 |
0 |
T1 |
464413 |
2 |
0 |
0 |
T2 |
81381 |
0 |
0 |
0 |
T3 |
660405 |
0 |
0 |
0 |
T4 |
1595 |
0 |
0 |
0 |
T5 |
1227 |
0 |
0 |
0 |
T6 |
40086 |
0 |
0 |
0 |
T7 |
295760 |
0 |
0 |
0 |
T8 |
6930 |
0 |
0 |
0 |
T9 |
196379 |
0 |
0 |
0 |
T10 |
1343 |
0 |
0 |
0 |
T27 |
0 |
29 |
0 |
0 |
T28 |
0 |
82 |
0 |
0 |
T146 |
0 |
22 |
0 |
0 |
T147 |
0 |
12 |
0 |
0 |
T148 |
0 |
38 |
0 |
0 |
T149 |
0 |
42 |
0 |
0 |
T150 |
0 |
19 |
0 |
0 |
T151 |
0 |
56 |
0 |
0 |
T152 |
0 |
24 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
2025 |
0 |
0 |
T68 |
36765 |
62 |
0 |
0 |
T69 |
66752 |
113 |
0 |
0 |
T114 |
5815 |
7 |
0 |
0 |
T115 |
9834 |
27 |
0 |
0 |
T122 |
6673 |
3 |
0 |
0 |
T123 |
11672 |
17 |
0 |
0 |
T134 |
8653 |
20 |
0 |
0 |
T143 |
37200 |
130 |
0 |
0 |
T144 |
181316 |
433 |
0 |
0 |
T145 |
90337 |
268 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1973 |
0 |
0 |
T68 |
36765 |
68 |
0 |
0 |
T69 |
66752 |
129 |
0 |
0 |
T114 |
5815 |
8 |
0 |
0 |
T115 |
9834 |
21 |
0 |
0 |
T122 |
6673 |
9 |
0 |
0 |
T123 |
11672 |
9 |
0 |
0 |
T134 |
8653 |
11 |
0 |
0 |
T143 |
37200 |
115 |
0 |
0 |
T144 |
181316 |
426 |
0 |
0 |
T145 |
90337 |
203 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1542 |
0 |
0 |
T68 |
36765 |
28 |
0 |
0 |
T69 |
66752 |
93 |
0 |
0 |
T114 |
5815 |
1 |
0 |
0 |
T115 |
9834 |
6 |
0 |
0 |
T122 |
6673 |
14 |
0 |
0 |
T123 |
11672 |
8 |
0 |
0 |
T134 |
8653 |
5 |
0 |
0 |
T143 |
37200 |
120 |
0 |
0 |
T144 |
181316 |
417 |
0 |
0 |
T145 |
90337 |
199 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1715 |
0 |
0 |
T68 |
36765 |
38 |
0 |
0 |
T69 |
66752 |
55 |
0 |
0 |
T114 |
5815 |
2 |
0 |
0 |
T115 |
9834 |
16 |
0 |
0 |
T122 |
6673 |
9 |
0 |
0 |
T123 |
11672 |
18 |
0 |
0 |
T134 |
8653 |
5 |
0 |
0 |
T143 |
37200 |
162 |
0 |
0 |
T144 |
181316 |
478 |
0 |
0 |
T145 |
90337 |
196 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1613 |
0 |
0 |
T68 |
36765 |
46 |
0 |
0 |
T69 |
66752 |
85 |
0 |
0 |
T114 |
5815 |
4 |
0 |
0 |
T115 |
9834 |
12 |
0 |
0 |
T122 |
6673 |
5 |
0 |
0 |
T123 |
11672 |
8 |
0 |
0 |
T134 |
8653 |
8 |
0 |
0 |
T143 |
37200 |
114 |
0 |
0 |
T144 |
181316 |
437 |
0 |
0 |
T145 |
90337 |
222 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1656 |
0 |
0 |
T68 |
36765 |
43 |
0 |
0 |
T69 |
66752 |
86 |
0 |
0 |
T114 |
5815 |
10 |
0 |
0 |
T115 |
9834 |
7 |
0 |
0 |
T122 |
6673 |
12 |
0 |
0 |
T123 |
11672 |
7 |
0 |
0 |
T134 |
8653 |
2 |
0 |
0 |
T143 |
37200 |
161 |
0 |
0 |
T144 |
181316 |
447 |
0 |
0 |
T145 |
90337 |
212 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
2590 |
0 |
0 |
T68 |
36765 |
95 |
0 |
0 |
T69 |
66752 |
191 |
0 |
0 |
T114 |
5815 |
6 |
0 |
0 |
T115 |
9834 |
24 |
0 |
0 |
T122 |
6673 |
22 |
0 |
0 |
T123 |
11672 |
23 |
0 |
0 |
T134 |
8653 |
37 |
0 |
0 |
T143 |
37200 |
163 |
0 |
0 |
T144 |
181316 |
521 |
0 |
0 |
T145 |
90337 |
230 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1707 |
0 |
0 |
T68 |
36765 |
34 |
0 |
0 |
T69 |
66752 |
77 |
0 |
0 |
T114 |
5815 |
7 |
0 |
0 |
T115 |
9834 |
14 |
0 |
0 |
T122 |
6673 |
15 |
0 |
0 |
T123 |
11672 |
9 |
0 |
0 |
T134 |
8653 |
4 |
0 |
0 |
T143 |
37200 |
114 |
0 |
0 |
T144 |
181316 |
448 |
0 |
0 |
T145 |
90337 |
249 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
2798 |
0 |
0 |
T68 |
36765 |
109 |
0 |
0 |
T69 |
66752 |
225 |
0 |
0 |
T114 |
5815 |
23 |
0 |
0 |
T115 |
9834 |
24 |
0 |
0 |
T122 |
6673 |
28 |
0 |
0 |
T123 |
11672 |
4 |
0 |
0 |
T134 |
8653 |
61 |
0 |
0 |
T143 |
37200 |
152 |
0 |
0 |
T144 |
181316 |
444 |
0 |
0 |
T145 |
90337 |
189 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1979 |
0 |
0 |
T68 |
36765 |
47 |
0 |
0 |
T69 |
66752 |
137 |
0 |
0 |
T114 |
5815 |
9 |
0 |
0 |
T115 |
9834 |
26 |
0 |
0 |
T122 |
6673 |
9 |
0 |
0 |
T123 |
11672 |
28 |
0 |
0 |
T134 |
8653 |
6 |
0 |
0 |
T143 |
37200 |
158 |
0 |
0 |
T144 |
181316 |
435 |
0 |
0 |
T145 |
90337 |
286 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1622 |
0 |
0 |
T68 |
36765 |
35 |
0 |
0 |
T69 |
66752 |
84 |
0 |
0 |
T114 |
5815 |
1 |
0 |
0 |
T115 |
9834 |
23 |
0 |
0 |
T122 |
6673 |
4 |
0 |
0 |
T123 |
11672 |
5 |
0 |
0 |
T134 |
8653 |
11 |
0 |
0 |
T143 |
37200 |
122 |
0 |
0 |
T144 |
181316 |
473 |
0 |
0 |
T145 |
90337 |
223 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1767 |
0 |
0 |
T68 |
36765 |
43 |
0 |
0 |
T69 |
66752 |
87 |
0 |
0 |
T114 |
5815 |
15 |
0 |
0 |
T115 |
9834 |
17 |
0 |
0 |
T123 |
11672 |
8 |
0 |
0 |
T125 |
4046 |
5 |
0 |
0 |
T134 |
8653 |
17 |
0 |
0 |
T143 |
37200 |
151 |
0 |
0 |
T144 |
181316 |
448 |
0 |
0 |
T145 |
90337 |
240 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1549 |
0 |
0 |
T68 |
36765 |
39 |
0 |
0 |
T69 |
66752 |
50 |
0 |
0 |
T114 |
5815 |
5 |
0 |
0 |
T115 |
9834 |
21 |
0 |
0 |
T122 |
6673 |
8 |
0 |
0 |
T123 |
11672 |
12 |
0 |
0 |
T134 |
8653 |
2 |
0 |
0 |
T143 |
37200 |
129 |
0 |
0 |
T144 |
181316 |
440 |
0 |
0 |
T145 |
90337 |
249 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1695 |
0 |
0 |
T68 |
36765 |
37 |
0 |
0 |
T69 |
66752 |
99 |
0 |
0 |
T114 |
5815 |
6 |
0 |
0 |
T115 |
9834 |
3 |
0 |
0 |
T122 |
6673 |
5 |
0 |
0 |
T123 |
11672 |
13 |
0 |
0 |
T134 |
8653 |
10 |
0 |
0 |
T143 |
37200 |
150 |
0 |
0 |
T144 |
181316 |
483 |
0 |
0 |
T145 |
90337 |
205 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1743 |
0 |
0 |
T68 |
36765 |
41 |
0 |
0 |
T69 |
66752 |
66 |
0 |
0 |
T114 |
5815 |
4 |
0 |
0 |
T115 |
9834 |
14 |
0 |
0 |
T122 |
6673 |
8 |
0 |
0 |
T123 |
11672 |
22 |
0 |
0 |
T134 |
8653 |
7 |
0 |
0 |
T143 |
37200 |
196 |
0 |
0 |
T144 |
181316 |
408 |
0 |
0 |
T145 |
90337 |
222 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455244826 |
1686 |
0 |
0 |
T68 |
36765 |
33 |
0 |
0 |
T69 |
66752 |
89 |
0 |
0 |
T114 |
5815 |
5 |
0 |
0 |
T115 |
9834 |
12 |
0 |
0 |
T122 |
6673 |
11 |
0 |
0 |
T123 |
11672 |
8 |
0 |
0 |
T134 |
8653 |
5 |
0 |
0 |
T143 |
37200 |
106 |
0 |
0 |
T144 |
181316 |
468 |
0 |
0 |
T145 |
90337 |
233 |
0 |
0 |