Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3736350	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4325419

1

T1

813

T2

23221

T3

3702

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4501436	1			T1	2221		T2	28193		T3	301
values[0x0]	1780497	1			T1	382		T2	11596		T3	1781
values[0x1]	1779836	1			T1	398		T2	11466		T3	1742

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2654667	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5407102

1

T1

1490

T2

31929

T3

3734

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31218	1			T1	10		T2	612		T3	27
valid_sources[0x01]	31158	1			T1	17		T2	439		T3	12
valid_sources[0x02]	28425	1			T1	12		T2	143		T3	8
valid_sources[0x03]	33906	1			T1	11		T2	3		T3	7
valid_sources[0x04]	30186	1			T1	15		T2	435		T3	21
valid_sources[0x05]	30669	1			T1	15		T2	88		T3	12
valid_sources[0x06]	29173	1			T1	8		T2	756		T3	12
valid_sources[0x07]	28973	1			T1	13		T2	140		T3	15
valid_sources[0x08]	31169	1			T1	10		T2	240		T3	19
valid_sources[0x09]	29140	1			T1	9		T2	163		T3	17
valid_sources[0x0a]	30954	1			T1	15		T2	670		T3	11
valid_sources[0x0b]	31740	1			T1	9		T2	250		T3	20
valid_sources[0x0c]	66691	1			T1	7		T2	50		T3	19
valid_sources[0x0d]	28989	1			T1	16		T2	148		T3	15
valid_sources[0x0e]	27991	1			T1	9		T2	90		T3	16
valid_sources[0x0f]	31522	1			T1	13		T2	443		T3	16
valid_sources[0x10]	29167	1			T1	10		T2	123		T3	10
valid_sources[0x11]	31362	1			T1	9		T2	1070		T3	25
valid_sources[0x12]	29814	1			T1	11		T2	297		T3	20
valid_sources[0x13]	31207	1			T1	13		T2	137		T3	16
valid_sources[0x14]	29917	1			T1	11		T2	212		T3	8
valid_sources[0x15]	31914	1			T1	15		T2	179		T3	4
valid_sources[0x16]	30782	1			T1	20		T2	380		T3	15
valid_sources[0x17]	29436	1			T1	11		T2	25		T3	8
valid_sources[0x18]	32101	1			T1	8		T2	143		T3	10
valid_sources[0x19]	38635	1			T1	10		T2	168		T3	16
valid_sources[0x1a]	31979	1			T1	13		T2	170		T3	16
valid_sources[0x1b]	29530	1			T1	14		T2	73		T3	19
valid_sources[0x1c]	30480	1			T1	12		T2	42		T3	13
valid_sources[0x1d]	27516	1			T1	12		T2	138		T3	17
valid_sources[0x1e]	36380	1			T1	18		T2	48		T3	19
valid_sources[0x1f]	32168	1			T1	9		T2	76		T3	24
valid_sources[0x20]	28176	1			T1	15		T2	233		T3	20
valid_sources[0x21]	40389	1			T1	11		T2	231		T3	22
valid_sources[0x22]	38916	1			T1	12		T2	113		T3	19
valid_sources[0x23]	29931	1			T1	13		T2	47		T3	13
valid_sources[0x24]	30711	1			T1	6		T2	27		T3	14
valid_sources[0x25]	30521	1			T1	10		T2	158		T3	11
valid_sources[0x26]	29603	1			T1	11		T2	133		T3	15
valid_sources[0x27]	35980	1			T1	9		T2	7		T3	11
valid_sources[0x28]	31220	1			T1	14		T2	172		T3	22
valid_sources[0x29]	32361	1			T1	8		T2	55		T3	17
valid_sources[0x2a]	32867	1			T1	13		T2	188		T3	8
valid_sources[0x2b]	31776	1			T1	8		T2	212		T3	25
valid_sources[0x2c]	29686	1			T1	10		T2	746		T3	18
valid_sources[0x2d]	30244	1			T1	14		T2	339		T3	13
valid_sources[0x2e]	28490	1			T1	14		T2	12		T3	17
valid_sources[0x2f]	29903	1			T1	16		T2	87		T3	23
valid_sources[0x30]	28146	1			T1	11		T2	2		T3	22
valid_sources[0x31]	28393	1			T1	15		T2	126		T3	13
valid_sources[0x32]	29919	1			T1	7		T2	174		T3	8
valid_sources[0x33]	32512	1			T1	15		T2	15		T3	13
valid_sources[0x34]	28918	1			T1	11		T2	63		T3	10
valid_sources[0x35]	30791	1			T1	18		T2	456		T3	16
valid_sources[0x36]	28035	1			T1	9		T2	115		T3	12
valid_sources[0x37]	31638	1			T1	7		T2	175		T3	15
valid_sources[0x38]	32379	1			T1	10		T2	791		T3	12
valid_sources[0x39]	29469	1			T1	4		T2	210		T3	9
valid_sources[0x3a]	36054	1			T1	19		T2	509		T3	18
valid_sources[0x3b]	32664	1			T1	14		T2	31		T3	21
valid_sources[0x3c]	32003	1			T1	5		T2	136		T3	24
valid_sources[0x3d]	31976	1			T1	9		T2	22		T3	16
valid_sources[0x3e]	33986	1			T1	11		T2	22		T3	21
valid_sources[0x3f]	28728	1			T1	6		T2	22		T3	11
valid_sources[0x40]	32872	1			T1	16		T2	31		T3	21
valid_sources[0x41]	33313	1			T1	13		T2	165		T3	10
valid_sources[0x42]	27114	1			T1	10		T2	50		T3	26
valid_sources[0x43]	31402	1			T1	11		T2	81		T3	18
valid_sources[0x44]	29367	1			T1	8		T2	94		T3	12
valid_sources[0x45]	31134	1			T1	13		T2	183		T3	14
valid_sources[0x46]	30970	1			T1	15		T2	127		T3	16
valid_sources[0x47]	29431	1			T1	12		T2	262		T3	16
valid_sources[0x48]	29374	1			T1	11		T2	23		T3	20
valid_sources[0x49]	28880	1			T1	18		T2	1		T3	14
valid_sources[0x4a]	31439	1			T1	12		T2	283		T3	18
valid_sources[0x4b]	32989	1			T1	10		T2	197		T3	1
valid_sources[0x4c]	33952	1			T1	7		T2	70		T3	14
valid_sources[0x4d]	30368	1			T1	18		T2	27		T3	19
valid_sources[0x4e]	30105	1			T1	3		T2	214		T3	10
valid_sources[0x4f]	32146	1			T1	12		T2	234		T3	16
valid_sources[0x50]	29896	1			T1	6		T2	305		T3	14
valid_sources[0x51]	33012	1			T1	7		T2	559		T3	11
valid_sources[0x52]	31055	1			T1	9		T2	168		T3	18
valid_sources[0x53]	35329	1			T1	14		T2	266		T3	26
valid_sources[0x54]	32273	1			T1	12		T2	67		T3	18
valid_sources[0x55]	37814	1			T1	8		T2	349		T3	14
valid_sources[0x56]	32389	1			T1	13		T2	120		T3	14
valid_sources[0x57]	32455	1			T1	11		T2	245		T3	12
valid_sources[0x58]	33103	1			T1	13		T2	6		T3	11
valid_sources[0x59]	31831	1			T1	10		T2	182		T3	20
valid_sources[0x5a]	33534	1			T1	10		T2	164		T3	10
valid_sources[0x5b]	28933	1			T1	15		T2	275		T3	20
valid_sources[0x5c]	28424	1			T1	10		T2	381		T3	11
valid_sources[0x5d]	30551	1			T1	12		T2	97		T3	13
valid_sources[0x5e]	31443	1			T1	18		T2	35		T3	12
valid_sources[0x5f]	32550	1			T1	18		T2	190		T3	25
valid_sources[0x60]	33564	1			T1	21		T2	746		T3	24
valid_sources[0x61]	29965	1			T1	12		T2	13		T3	11
valid_sources[0x62]	31890	1			T1	14		T2	50		T3	13
valid_sources[0x63]	30149	1			T1	11		T2	125		T3	18
valid_sources[0x64]	29984	1			T1	17		T2	53		T3	18
valid_sources[0x65]	29220	1			T1	12		T2	741		T3	15
valid_sources[0x66]	35693	1			T1	15		T2	23		T3	21
valid_sources[0x67]	27754	1			T1	14		T2	47		T3	16
valid_sources[0x68]	28972	1			T1	16		T2	3		T3	16
valid_sources[0x69]	38170	1			T1	13		T2	144		T3	9
valid_sources[0x6a]	31901	1			T1	15		T2	272		T3	14
valid_sources[0x6b]	28660	1			T1	16		T2	227		T3	14
valid_sources[0x6c]	33170	1			T1	9		T2	142		T3	12
valid_sources[0x6d]	27377	1			T1	15		T2	227		T3	17
valid_sources[0x6e]	36797	1			T1	12		T2	13		T3	7
valid_sources[0x6f]	29958	1			T1	17		T2	67		T3	25
valid_sources[0x70]	34084	1			T1	10		T2	190		T3	21
valid_sources[0x71]	35773	1			T1	7		T2	244		T3	10
valid_sources[0x72]	32462	1			T1	11		T2	229		T3	21
valid_sources[0x73]	29169	1			T1	11		T2	103		T3	14
valid_sources[0x74]	29026	1			T1	14		T2	333		T3	14
valid_sources[0x75]	30617	1			T1	12		T2	228		T3	10
valid_sources[0x76]	32153	1			T1	7		T2	1023		T3	15
valid_sources[0x77]	31597	1			T1	7		T2	39		T3	10
valid_sources[0x78]	38288	1			T1	5		T2	68		T3	18
valid_sources[0x79]	31498	1			T1	13		T2	56		T3	13
valid_sources[0x7a]	39121	1			T1	8		T2	87		T3	13
valid_sources[0x7b]	29112	1			T1	8		T2	400		T3	5
valid_sources[0x7c]	30753	1			T1	9		T2	106		T3	15
valid_sources[0x7d]	33167	1			T1	10		T2	187		T3	9
valid_sources[0x7e]	31357	1			T1	12		T2	95		T3	20
valid_sources[0x7f]	28023	1			T1	13		T2	988		T3	7
valid_sources[0x80]	35329	1			T1	7		T2	569		T3	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1106400

1

T1

278

T2

2816

T3

197

values[0x0]

all_enables

biggest_size

1621955

1

T1

264

T2

10346

T3

1776

values[0x1]

all_enables

biggest_size

1597064

1

T1

271

T2

10059

T3

1729