Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3753917

1

T1

2188

T2

28034

T3

122

full_word

4326426

1

T1

813

T2

23221

T3

3702

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8079923	1			T1	3001		T2	51255		T3	3824
auto[TlIntgErrCmd]	118	1			T70	3		T88	12		T89	3
auto[TlIntgErrData]	166	1			T70	10		T88	9		T89	5
auto[TlIntgErrBoth]	136	1			T70	7		T88	9		T89	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4504924

1

T1

2221

T2

28193

T3

301

auto[1]

3575419

1

T1

780

T2

23062

T3

3523

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3398077	1			T1	1943		T2	25377		T3	104
auto[TlIntgErrNone]	partial	auto[1]	355448	1			T1	245		T2	2657		T3	18
auto[TlIntgErrNone]	full_word	auto[0]	1106638	1			T1	278		T2	2816		T3	197
auto[TlIntgErrNone]	full_word	auto[1]	3219760	1			T1	535		T2	20405		T3	3505
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T70	2		T88	4		T89	1
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T70	1		T88	6		T89	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T171	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T88	2		T172	2		-	-
auto[TlIntgErrData]	partial	auto[0]	86	1			T70	5		T88	5		T89	3
auto[TlIntgErrData]	partial	auto[1]	66	1			T70	4		T88	3		T89	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T100	1		T101	1		T171	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T70	1		T88	1		T98	1
auto[TlIntgErrBoth]	partial	auto[0]	60	1			T70	3		T88	5		T89	2
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T70	3		T88	2		T98	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T70	1		T173	1		T172	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T88	2		T147	1		T101	1