Group : spi_device_env_pkg::busy_blocks_command_cg
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Group : spi_device_env_pkg::busy_blocks_command_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

5 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
spi_device_env_pkg.en4b_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.ex4b_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.upload_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.wrdi_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.wren_block_cmd_cg 100.00 1 100 1 64 64




Group Instance : spi_device_env_pkg.en4b_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.en4b_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.en4b_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.ex4b_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.ex4b_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.ex4b_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.upload_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.upload_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.upload_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.wrdi_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.wrdi_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.wrdi_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.wren_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.wren_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.wren_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 28 1 T32 1 T82 2 T159 1
allowed 1550 1 T2 8 T3 1 T6 8


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 24 1 T82 1 T83 3 T174 1
allowed 1551 1 T2 9 T3 4 T6 11


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 184 1 T42 4 T82 4 T83 4
allowed 4816 1 T2 32 T3 8 T6 20


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 27 1 T144 2 T57 1 T59 2
allowed 1401 1 T2 11 T3 3 T6 6


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 24 1 T42 3 T83 1 T174 1
allowed 1442 1 T2 5 T3 3 T6 15

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