Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	439684255	2813973	0	0
DepthKnown_A	439684255	439554223	0	0
RvalidKnown_A	439684255	439554223	0	0
WreadyKnown_A	439684255	439554223	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	2813973	0	0
T2	269112	14138	0	0
T3	71449	4990	0	0
T4	6302	0	0	0
T5	4678	0	0	0
T6	350803	14155	0	0
T7	5303	0	0	0
T8	192812	832	0	0
T9	914	0	0	0
T10	417089	19961	0	0
T11	332471	0	0	0
T12	0	832	0	0
T13	0	1663	0	0
T14	0	1663	0	0
T16	0	4158	0	0
T17	0	4990	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	439684255	3226221	0	0
DepthKnown_A	439684255	439554223	0	0
RvalidKnown_A	439684255	439554223	0	0
WreadyKnown_A	439684255	439554223	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	3226221	0	0
T2	269112	9152	0	0
T3	71449	3328	0	0
T4	6302	0	0	0
T5	4678	0	0	0
T6	350803	17875	0	0
T7	5303	0	0	0
T8	192812	3684	0	0
T9	914	0	0	0
T10	417089	14144	0	0
T11	332471	0	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T16	0	2496	0	0
T17	0	6855	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	439684255	189474	0	0
DepthKnown_A	439684255	439554223	0	0
RvalidKnown_A	439684255	439554223	0	0
WreadyKnown_A	439684255	439554223	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	189474	0	0
T1	161848	232	0	0
T2	269112	752	0	0
T3	71449	120	0	0
T4	6302	23	0	0
T5	4678	0	0	0
T6	350803	458	0	0
T7	5303	0	0	0
T8	192812	0	0	0
T9	914	0	0	0
T10	417089	599	0	0
T16	0	495	0	0
T17	0	240	0	0
T23	0	409	0	0
T25	0	1060	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	439684255	436532	0	0
DepthKnown_A	439684255	439554223	0	0
RvalidKnown_A	439684255	439554223	0	0
WreadyKnown_A	439684255	439554223	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	436532	0	0
T1	161848	232	0	0
T2	269112	752	0	0
T3	71449	120	0	0
T4	6302	23	0	0
T5	4678	0	0	0
T6	350803	1498	0	0
T7	5303	0	0	0
T8	192812	0	0	0
T9	914	0	0	0
T10	417089	599	0	0
T16	0	495	0	0
T17	0	795	0	0
T23	0	409	0	0
T25	0	1060	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	439684255	6444990	0	0
DepthKnown_A	439684255	439554223	0	0
RvalidKnown_A	439684255	439554223	0	0
WreadyKnown_A	439684255	439554223	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	6444990	0	0
T1	161848	2790	0	0
T2	269112	41665	0	0
T3	71449	376	0	0
T4	6302	785	0	0
T5	4678	1	0	0
T6	350803	17683	0	0
T7	5303	25	0	0
T8	192812	355	0	0
T9	914	18	0	0
T10	417089	4621	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	439684255	13071557	0	0
DepthKnown_A	439684255	439554223	0	0
RvalidKnown_A	439684255	439554223	0	0
WreadyKnown_A	439684255	439554223	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	13071557	0	0
T1	161848	2769	0	0
T2	269112	41351	0	0
T3	71449	376	0	0
T4	6302	785	0	0
T5	4678	1	0	0
T6	350803	51792	0	0
T7	5303	25	0	0
T8	192812	1483	0	0
T9	914	73	0	0
T10	417089	4592	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439684255	439554223	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0