Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T2,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	730553340	582361243	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	730553340	3684585	0	0
GntImpliesValid_A	730553340	3684585	0	0
GrantKnown_A	730553340	582361243	0	0
IdxKnown_A	730553340	582361243	0	0
IndexIsCorrect_A	730553340	3684585	0	0
LockArbDecision_A	730553340	0	0	0
NoReadyValidNoGrant_A	730553340	0	0	0
ReadyAndValidImplyGrant_A	730553340	3684585	0	0
ReqAndReadyImplyGrant_A	730553340	3684585	0	0
ReqImpliesValid_A	730553340	3684585	0	0
ReqStaysHighUntilGranted0_M	730553340	0	0	0
RoundRobin_A	730553340	7	0	956
ValidKnown_A	730553340	582361243	0	0
gen_data_port_assertion.DataFlow_A	730553340	3684585	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730553340	582361243	0	0
T1	188974	187816	0	0
T2	1155676	707830	0	0
T3	346555	208799	0	0
T4	16446	11299	0	0
T5	4678	3888	0	0
T6	1218659	781197	0	0
T7	8079	5821	0	0
T8	238566	214922	0	0
T9	914	849	0	0
T10	1960569	1181965	0	0
T11	220326	103128	0	0
T12	65372	32686	0	0
T13	66369	65868	0	0
T14	0	126416	0	0
T16	0	127407	0	0
T17	0	337126	0	0
T23	0	66368	0	0
T24	0	936	0	0
T25	0	448488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730553340	3684585	0	0
T1	188974	1585	0	0
T2	1155676	19111	0	0
T3	346555	3947	0	0
T4	16446	335	0	0
T5	4678	0	0	0
T6	1218659	18062	0	0
T7	8079	0	0	0
T8	238566	832	0	0
T9	914	0	0	0
T10	1960569	18491	0	0
T11	220326	0	0	0
T12	65372	832	0	0
T13	66369	832	0	0
T16	0	4949	0	0
T17	0	4792	0	0
T23	0	3592	0	0
T25	0	5983	0	0
T31	0	644	0	0
T40	0	914	0	0
T41	0	908	0	0
T48	0	3222	0	0
T50	0	1790	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730553340	3684585	0	0
T1	188974	1585	0	0
T2	1155676	19111	0	0
T3	346555	3947	0	0
T4	16446	335	0	0
T5	4678	0	0	0
T6	1218659	18062	0	0
T7	8079	0	0	0
T8	238566	832	0	0
T9	914	0	0	0
T10	1960569	18491	0	0
T11	220326	0	0	0
T12	65372	832	0	0
T13	66369	832	0	0
T16	0	4949	0	0
T17	0	4792	0	0
T23	0	3592	0	0
T25	0	5983	0	0
T31	0	644	0	0
T40	0	914	0	0
T41	0	908	0	0
T48	0	3222	0	0
T50	0	1790	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730553340	582361243	0	0
T1	188974	187816	0	0
T2	1155676	707830	0	0
T3	346555	208799	0	0
T4	16446	11299	0	0
T5	4678	3888	0	0
T6	1218659	781197	0	0
T7	8079	5821	0	0
T8	238566	214922	0	0
T9	914	849	0	0
T10	1960569	1181965	0	0
T11	220326	103128	0	0
T12	65372	32686	0	0
T13	66369	65868	0	0
T14	0	126416	0	0
T16	0	127407	0	0
T17	0	337126	0	0
T23	0	66368	0	0
T24	0	936	0	0
T25	0	448488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730553340	582361243	0	0
T1	188974	187816	0	0
T2	1155676	707830	0	0
T3	346555	208799	0	0
T4	16446	11299	0	0
T5	4678	3888	0	0
T6	1218659	781197	0	0
T7	8079	5821	0	0
T8	238566	214922	0	0
T9	914	849	0	0
T10	1960569	1181965	0	0
T11	220326	103128	0	0
T12	65372	32686	0	0
T13	66369	65868	0	0
T14	0	126416	0	0
T16	0	127407	0	0
T17	0	337126	0	0
T23	0	66368	0	0
T24	0	936	0	0
T25	0	448488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730553340	3684585	0	0
T1	188974	1585	0	0
T2	1155676	19111	0	0
T3	346555	3947	0	0
T4	16446	335	0	0
T5	4678	0	0	0
T6	1218659	18062	0	0
T7	8079	0	0	0
T8	238566	832	0	0
T9	914	0	0	0
T10	1960569	18491	0	0
T11	220326	0	0	0
T12	65372	832	0	0
T13	66369	832	0	0
T16	0	4949	0	0
T17	0	4792	0	0
T23	0	3592	0	0
T25	0	5983	0	0
T31	0	644	0	0
T40	0	914	0	0
T41	0	908	0	0
T48	0	3222	0	0
T50	0	1790	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730553340	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730553340	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730553340	3684585	0	0
T1	188974	1585	0	0
T2	1155676	19111	0	0
T3	346555	3947	0	0
T4	16446	335	0	0
T5	4678	0	0	0
T6	1218659	18062	0	0
T7	8079	0	0	0
T8	238566	832	0	0
T9	914	0	0	0
T10	1960569	18491	0	0
T11	220326	0	0	0
T12	65372	832	0	0
T13	66369	832	0	0
T16	0	4949	0	0
T17	0	4792	0	0
T23	0	3592	0	0
T25	0	5983	0	0
T31	0	644	0	0
T40	0	914	0	0
T41	0	908	0	0
T48	0	3222	0	0
T50	0	1790	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730553340	3684585	0	0
T1	188974	1585	0	0
T2	1155676	19111	0	0
T3	346555	3947	0	0
T4	16446	335	0	0
T5	4678	0	0	0
T6	1218659	18062	0	0
T7	8079	0	0	0
T8	238566	832	0	0
T9	914	0	0	0
T10	1960569	18491	0	0
T11	220326	0	0	0
T12	65372	832	0	0
T13	66369	832	0	0
T16	0	4949	0	0
T17	0	4792	0	0
T23	0	3592	0	0
T25	0	5983	0	0
T31	0	644	0	0
T40	0	914	0	0
T41	0	908	0	0
T48	0	3222	0	0
T50	0	1790	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730553340	3684585	0	0
T1	188974	1585	0	0
T2	1155676	19111	0	0
T3	346555	3947	0	0
T4	16446	335	0	0
T5	4678	0	0	0
T6	1218659	18062	0	0
T7	8079	0	0	0
T8	238566	832	0	0
T9	914	0	0	0
T10	1960569	18491	0	0
T11	220326	0	0	0
T12	65372	832	0	0
T13	66369	832	0	0
T16	0	4949	0	0
T17	0	4792	0	0
T23	0	3592	0	0
T25	0	5983	0	0
T31	0	644	0	0
T40	0	914	0	0
T41	0	908	0	0
T48	0	3222	0	0
T50	0	1790	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	730553340	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730553340	7	0	956
T30	0	1	0	0
T51	236909	2	0	1
T52	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	189953	0	0	1
T56	258430	0	0	1
T57	198933	0	0	1
T58	1752	0	0	1
T59	202794	0	0	1
T60	97177	0	0	1
T61	31029	0	0	1
T62	142561	0	0	1
T63	1135	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730553340	582361243	0	0
T1	188974	187816	0	0
T2	1155676	707830	0	0
T3	346555	208799	0	0
T4	16446	11299	0	0
T5	4678	3888	0	0
T6	1218659	781197	0	0
T7	8079	5821	0	0
T8	238566	214922	0	0
T9	914	849	0	0
T10	1960569	1181965	0	0
T11	220326	103128	0	0
T12	65372	32686	0	0
T13	66369	65868	0	0
T14	0	126416	0	0
T16	0	127407	0	0
T17	0	337126	0	0
T23	0	66368	0	0
T24	0	936	0	0
T25	0	448488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730553340	3684585	0	0
T1	188974	1585	0	0
T2	1155676	19111	0	0
T3	346555	3947	0	0
T4	16446	335	0	0
T5	4678	0	0	0
T6	1218659	18062	0	0
T7	8079	0	0	0
T8	238566	832	0	0
T9	914	0	0	0
T10	1960569	18491	0	0
T11	220326	0	0	0
T12	65372	832	0	0
T13	66369	832	0	0
T16	0	4949	0	0
T17	0	4792	0	0
T23	0	3592	0	0
T25	0	5983	0	0
T31	0	644	0	0
T40	0	914	0	0
T41	0	908	0	0
T48	0	3222	0	0
T50	0	1790	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	146748842	28722354	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	146748842	638765	0	0
GntImpliesValid_A	146748842	638765	0	0
GrantKnown_A	146748842	28722354	0	0
IdxKnown_A	146748842	28722354	0	0
IndexIsCorrect_A	146748842	638765	0	0
LockArbDecision_A	146748842	0	0	0
NoReadyValidNoGrant_A	146748842	0	0	0
ReadyAndValidImplyGrant_A	146748842	638765	0	0
ReqAndReadyImplyGrant_A	146748842	638765	0	0
ReqImpliesValid_A	146748842	638765	0	0
ReqStaysHighUntilGranted0_M	146748842	0	0	0
RoundRobin_A	146748842	0	0	0
ValidKnown_A	146748842	28722354	0	0
gen_data_port_assertion.DataFlow_A	146748842	638765	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	28722354	0	0
T1	27126	26064	0	0
T2	443282	52192	0	0
T3	137553	0	0	0
T4	5072	5072	0	0
T6	433928	12424	0	0
T7	1388	576	0	0
T8	22877	0	0	0
T10	771740	95920	0	0
T11	110163	103128	0	0
T12	32686	0	0	0
T23	0	66368	0	0
T24	0	936	0	0
T25	0	448488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	638765	0	0
T1	27126	1137	0	0
T2	443282	2442	0	0
T3	137553	0	0	0
T4	5072	202	0	0
T6	433928	590	0	0
T7	1388	0	0	0
T8	22877	0	0	0
T10	771740	1180	0	0
T11	110163	0	0	0
T12	32686	0	0	0
T16	0	1457	0	0
T17	0	511	0	0
T23	0	2417	0	0
T25	0	5983	0	0
T48	0	3222	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	638765	0	0
T1	27126	1137	0	0
T2	443282	2442	0	0
T3	137553	0	0	0
T4	5072	202	0	0
T6	433928	590	0	0
T7	1388	0	0	0
T8	22877	0	0	0
T10	771740	1180	0	0
T11	110163	0	0	0
T12	32686	0	0	0
T16	0	1457	0	0
T17	0	511	0	0
T23	0	2417	0	0
T25	0	5983	0	0
T48	0	3222	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	28722354	0	0
T1	27126	26064	0	0
T2	443282	52192	0	0
T3	137553	0	0	0
T4	5072	5072	0	0
T6	433928	12424	0	0
T7	1388	576	0	0
T8	22877	0	0	0
T10	771740	95920	0	0
T11	110163	103128	0	0
T12	32686	0	0	0
T23	0	66368	0	0
T24	0	936	0	0
T25	0	448488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	28722354	0	0
T1	27126	26064	0	0
T2	443282	52192	0	0
T3	137553	0	0	0
T4	5072	5072	0	0
T6	433928	12424	0	0
T7	1388	576	0	0
T8	22877	0	0	0
T10	771740	95920	0	0
T11	110163	103128	0	0
T12	32686	0	0	0
T23	0	66368	0	0
T24	0	936	0	0
T25	0	448488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	638765	0	0
T1	27126	1137	0	0
T2	443282	2442	0	0
T3	137553	0	0	0
T4	5072	202	0	0
T6	433928	590	0	0
T7	1388	0	0	0
T8	22877	0	0	0
T10	771740	1180	0	0
T11	110163	0	0	0
T12	32686	0	0	0
T16	0	1457	0	0
T17	0	511	0	0
T23	0	2417	0	0
T25	0	5983	0	0
T48	0	3222	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	638765	0	0
T1	27126	1137	0	0
T2	443282	2442	0	0
T3	137553	0	0	0
T4	5072	202	0	0
T6	433928	590	0	0
T7	1388	0	0	0
T8	22877	0	0	0
T10	771740	1180	0	0
T11	110163	0	0	0
T12	32686	0	0	0
T16	0	1457	0	0
T17	0	511	0	0
T23	0	2417	0	0
T25	0	5983	0	0
T48	0	3222	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	638765	0	0
T1	27126	1137	0	0
T2	443282	2442	0	0
T3	137553	0	0	0
T4	5072	202	0	0
T6	433928	590	0	0
T7	1388	0	0	0
T8	22877	0	0	0
T10	771740	1180	0	0
T11	110163	0	0	0
T12	32686	0	0	0
T16	0	1457	0	0
T17	0	511	0	0
T23	0	2417	0	0
T25	0	5983	0	0
T48	0	3222	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	638765	0	0
T1	27126	1137	0	0
T2	443282	2442	0	0
T3	137553	0	0	0
T4	5072	202	0	0
T6	433928	590	0	0
T7	1388	0	0	0
T8	22877	0	0	0
T10	771740	1180	0	0
T11	110163	0	0	0
T12	32686	0	0	0
T16	0	1457	0	0
T17	0	511	0	0
T23	0	2417	0	0
T25	0	5983	0	0
T48	0	3222	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	28722354	0	0
T1	27126	26064	0	0
T2	443282	52192	0	0
T3	137553	0	0	0
T4	5072	5072	0	0
T6	433928	12424	0	0
T7	1388	576	0	0
T8	22877	0	0	0
T10	771740	95920	0	0
T11	110163	103128	0	0
T12	32686	0	0	0
T23	0	66368	0	0
T24	0	936	0	0
T25	0	448488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	638765	0	0
T1	27126	1137	0	0
T2	443282	2442	0	0
T3	137553	0	0	0
T4	5072	202	0	0
T6	433928	590	0	0
T7	1388	0	0	0
T8	22877	0	0	0
T10	771740	1180	0	0
T11	110163	0	0	0
T12	32686	0	0	0
T16	0	1457	0	0
T17	0	511	0	0
T23	0	2417	0	0
T25	0	5983	0	0
T48	0	3222	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T2,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T6
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	146748842	116666226	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	146748842	798060	0	0
GntImpliesValid_A	146748842	798060	0	0
GrantKnown_A	146748842	116666226	0	0
IdxKnown_A	146748842	116666226	0	0
IndexIsCorrect_A	146748842	798060	0	0
LockArbDecision_A	146748842	0	0	0
NoReadyValidNoGrant_A	146748842	0	0	0
ReadyAndValidImplyGrant_A	146748842	798060	0	0
ReqAndReadyImplyGrant_A	146748842	798060	0	0
ReqImpliesValid_A	146748842	798060	0	0
ReqStaysHighUntilGranted0_M	146748842	0	0	0
RoundRobin_A	146748842	0	0	0
ValidKnown_A	146748842	116666226	0	0
gen_data_port_assertion.DataFlow_A	146748842	798060	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	116666226	0	0
T2	443282	386532	0	0
T3	137553	137428	0	0
T4	5072	0	0	0
T6	433928	417975	0	0
T7	1388	0	0	0
T8	22877	22206	0	0
T10	771740	669141	0	0
T11	110163	0	0	0
T12	32686	32686	0	0
T13	66369	65868	0	0
T14	0	126416	0	0
T16	0	127407	0	0
T17	0	337126	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	798060	0	0
T2	443282	6053	0	0
T3	137553	491	0	0
T4	5072	0	0	0
T6	433928	7689	0	0
T7	1388	0	0	0
T8	22877	0	0	0
T10	771740	2051	0	0
T11	110163	0	0	0
T12	32686	0	0	0
T13	66369	0	0	0
T16	0	3492	0	0
T17	0	4281	0	0
T31	0	644	0	0
T40	0	914	0	0
T41	0	908	0	0
T50	0	1790	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	798060	0	0
T2	443282	6053	0	0
T3	137553	491	0	0
T4	5072	0	0	0
T6	433928	7689	0	0
T7	1388	0	0	0
T8	22877	0	0	0
T10	771740	2051	0	0
T11	110163	0	0	0
T12	32686	0	0	0
T13	66369	0	0	0
T16	0	3492	0	0
T17	0	4281	0	0
T31	0	644	0	0
T40	0	914	0	0
T41	0	908	0	0
T50	0	1790	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	116666226	0	0
T2	443282	386532	0	0
T3	137553	137428	0	0
T4	5072	0	0	0
T6	433928	417975	0	0
T7	1388	0	0	0
T8	22877	22206	0	0
T10	771740	669141	0	0
T11	110163	0	0	0
T12	32686	32686	0	0
T13	66369	65868	0	0
T14	0	126416	0	0
T16	0	127407	0	0
T17	0	337126	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	116666226	0	0
T2	443282	386532	0	0
T3	137553	137428	0	0
T4	5072	0	0	0
T6	433928	417975	0	0
T7	1388	0	0	0
T8	22877	22206	0	0
T10	771740	669141	0	0
T11	110163	0	0	0
T12	32686	32686	0	0
T13	66369	65868	0	0
T14	0	126416	0	0
T16	0	127407	0	0
T17	0	337126	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	798060	0	0
T2	443282	6053	0	0
T3	137553	491	0	0
T4	5072	0	0	0
T6	433928	7689	0	0
T7	1388	0	0	0
T8	22877	0	0	0
T10	771740	2051	0	0
T11	110163	0	0	0
T12	32686	0	0	0
T13	66369	0	0	0
T16	0	3492	0	0
T17	0	4281	0	0
T31	0	644	0	0
T40	0	914	0	0
T41	0	908	0	0
T50	0	1790	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	798060	0	0
T2	443282	6053	0	0
T3	137553	491	0	0
T4	5072	0	0	0
T6	433928	7689	0	0
T7	1388	0	0	0
T8	22877	0	0	0
T10	771740	2051	0	0
T11	110163	0	0	0
T12	32686	0	0	0
T13	66369	0	0	0
T16	0	3492	0	0
T17	0	4281	0	0
T31	0	644	0	0
T40	0	914	0	0
T41	0	908	0	0
T50	0	1790	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	798060	0	0
T2	443282	6053	0	0
T3	137553	491	0	0
T4	5072	0	0	0
T6	433928	7689	0	0
T7	1388	0	0	0
T8	22877	0	0	0
T10	771740	2051	0	0
T11	110163	0	0	0
T12	32686	0	0	0
T13	66369	0	0	0
T16	0	3492	0	0
T17	0	4281	0	0
T31	0	644	0	0
T40	0	914	0	0
T41	0	908	0	0
T50	0	1790	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	798060	0	0
T2	443282	6053	0	0
T3	137553	491	0	0
T4	5072	0	0	0
T6	433928	7689	0	0
T7	1388	0	0	0
T8	22877	0	0	0
T10	771740	2051	0	0
T11	110163	0	0	0
T12	32686	0	0	0
T13	66369	0	0	0
T16	0	3492	0	0
T17	0	4281	0	0
T31	0	644	0	0
T40	0	914	0	0
T41	0	908	0	0
T50	0	1790	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	116666226	0	0
T2	443282	386532	0	0
T3	137553	137428	0	0
T4	5072	0	0	0
T6	433928	417975	0	0
T7	1388	0	0	0
T8	22877	22206	0	0
T10	771740	669141	0	0
T11	110163	0	0	0
T12	32686	32686	0	0
T13	66369	65868	0	0
T14	0	126416	0	0
T16	0	127407	0	0
T17	0	337126	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146748842	798060	0	0
T2	443282	6053	0	0
T3	137553	491	0	0
T4	5072	0	0	0
T6	433928	7689	0	0
T7	1388	0	0	0
T8	22877	0	0	0
T10	771740	2051	0	0
T11	110163	0	0	0
T12	32686	0	0	0
T13	66369	0	0	0
T16	0	3492	0	0
T17	0	4281	0	0
T31	0	644	0	0
T40	0	914	0	0
T41	0	908	0	0
T50	0	1790	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437055656	436972663	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	437055656	2247760	0	0
GntImpliesValid_A	437055656	2247760	0	0
GrantKnown_A	437055656	436972663	0	0
IdxKnown_A	437055656	436972663	0	0
IndexIsCorrect_A	437055656	2247760	0	0
LockArbDecision_A	437055656	0	0	0
NoReadyValidNoGrant_A	437055656	0	0	0
ReadyAndValidImplyGrant_A	437055656	2247760	0	0
ReqAndReadyImplyGrant_A	437055656	2247760	0	0
ReqImpliesValid_A	437055656	2247760	0	0
ReqStaysHighUntilGranted0_M	437055656	0	0	0
RoundRobin_A	437055656	7	0	956
ValidKnown_A	437055656	436972663	0	0
gen_data_port_assertion.DataFlow_A	437055656	2247760	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437055656	436972663	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437055656	2247760	0	0
T1	161848	448	0	0
T2	269112	10616	0	0
T3	71449	3456	0	0
T4	6302	133	0	0
T5	4678	0	0	0
T6	350803	9783	0	0
T7	5303	0	0	0
T8	192812	832	0	0
T9	914	0	0	0
T10	417089	15260	0	0
T12	0	832	0	0
T13	0	832	0	0
T23	0	1175	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437055656	2247760	0	0
T1	161848	448	0	0
T2	269112	10616	0	0
T3	71449	3456	0	0
T4	6302	133	0	0
T5	4678	0	0	0
T6	350803	9783	0	0
T7	5303	0	0	0
T8	192812	832	0	0
T9	914	0	0	0
T10	417089	15260	0	0
T12	0	832	0	0
T13	0	832	0	0
T23	0	1175	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437055656	436972663	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437055656	436972663	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437055656	2247760	0	0
T1	161848	448	0	0
T2	269112	10616	0	0
T3	71449	3456	0	0
T4	6302	133	0	0
T5	4678	0	0	0
T6	350803	9783	0	0
T7	5303	0	0	0
T8	192812	832	0	0
T9	914	0	0	0
T10	417089	15260	0	0
T12	0	832	0	0
T13	0	832	0	0
T23	0	1175	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437055656	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437055656	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437055656	2247760	0	0
T1	161848	448	0	0
T2	269112	10616	0	0
T3	71449	3456	0	0
T4	6302	133	0	0
T5	4678	0	0	0
T6	350803	9783	0	0
T7	5303	0	0	0
T8	192812	832	0	0
T9	914	0	0	0
T10	417089	15260	0	0
T12	0	832	0	0
T13	0	832	0	0
T23	0	1175	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437055656	2247760	0	0
T1	161848	448	0	0
T2	269112	10616	0	0
T3	71449	3456	0	0
T4	6302	133	0	0
T5	4678	0	0	0
T6	350803	9783	0	0
T7	5303	0	0	0
T8	192812	832	0	0
T9	914	0	0	0
T10	417089	15260	0	0
T12	0	832	0	0
T13	0	832	0	0
T23	0	1175	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437055656	2247760	0	0
T1	161848	448	0	0
T2	269112	10616	0	0
T3	71449	3456	0	0
T4	6302	133	0	0
T5	4678	0	0	0
T6	350803	9783	0	0
T7	5303	0	0	0
T8	192812	832	0	0
T9	914	0	0	0
T10	417089	15260	0	0
T12	0	832	0	0
T13	0	832	0	0
T23	0	1175	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437055656	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437055656	7	0	956
T30	0	1	0	0
T51	236909	2	0	1
T52	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	189953	0	0	1
T56	258430	0	0	1
T57	198933	0	0	1
T58	1752	0	0	1
T59	202794	0	0	1
T60	97177	0	0	1
T61	31029	0	0	1
T62	142561	0	0	1
T63	1135	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437055656	436972663	0	0
T1	161848	161752	0	0
T2	269112	269106	0	0
T3	71449	71371	0	0
T4	6302	6227	0	0
T5	4678	3888	0	0
T6	350803	350798	0	0
T7	5303	5245	0	0
T8	192812	192716	0	0
T9	914	849	0	0
T10	417089	416904	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437055656	2247760	0	0
T1	161848	448	0	0
T2	269112	10616	0	0
T3	71449	3456	0	0
T4	6302	133	0	0
T5	4678	0	0	0
T6	350803	9783	0	0
T7	5303	0	0	0
T8	192812	832	0	0
T9	914	0	0	0
T10	417089	15260	0	0
T12	0	832	0	0
T13	0	832	0	0
T23	0	1175	0	0