Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
2442 | 
0 | 
0 | 
| T68 | 
3799 | 
8 | 
0 | 
0 | 
| T69 | 
18348 | 
140 | 
0 | 
0 | 
| T70 | 
66818 | 
2 | 
0 | 
0 | 
| T86 | 
8750 | 
61 | 
0 | 
0 | 
| T87 | 
5624 | 
238 | 
0 | 
0 | 
| T88 | 
81033 | 
5 | 
0 | 
0 | 
| T89 | 
10357 | 
3 | 
0 | 
0 | 
| T93 | 
2777 | 
3 | 
0 | 
0 | 
| T97 | 
5302 | 
9 | 
0 | 
0 | 
| T98 | 
80850 | 
3 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3260 | 
0 | 
0 | 
| T70 | 
66818 | 
51 | 
0 | 
0 | 
| T101 | 
93985 | 
44 | 
0 | 
0 | 
| T105 | 
9304 | 
2 | 
0 | 
0 | 
| T106 | 
111689 | 
730 | 
0 | 
0 | 
| T110 | 
7879 | 
8 | 
0 | 
0 | 
| T132 | 
19576 | 
19 | 
0 | 
0 | 
| T133 | 
7227 | 
13 | 
0 | 
0 | 
| T145 | 
124392 | 
751 | 
0 | 
0 | 
| T146 | 
21400 | 
101 | 
0 | 
0 | 
| T147 | 
63943 | 
79 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3515 | 
0 | 
0 | 
| T70 | 
66818 | 
75 | 
0 | 
0 | 
| T101 | 
93985 | 
60 | 
0 | 
0 | 
| T103 | 
6387 | 
3 | 
0 | 
0 | 
| T106 | 
111689 | 
829 | 
0 | 
0 | 
| T110 | 
7879 | 
15 | 
0 | 
0 | 
| T132 | 
19576 | 
71 | 
0 | 
0 | 
| T133 | 
7227 | 
13 | 
0 | 
0 | 
| T145 | 
124392 | 
780 | 
0 | 
0 | 
| T146 | 
21400 | 
74 | 
0 | 
0 | 
| T147 | 
63943 | 
80 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3830 | 
0 | 
0 | 
| T70 | 
66818 | 
233 | 
0 | 
0 | 
| T101 | 
93985 | 
118 | 
0 | 
0 | 
| T103 | 
6387 | 
8 | 
0 | 
0 | 
| T105 | 
9304 | 
8 | 
0 | 
0 | 
| T106 | 
111689 | 
748 | 
0 | 
0 | 
| T132 | 
19576 | 
17 | 
0 | 
0 | 
| T133 | 
7227 | 
8 | 
0 | 
0 | 
| T145 | 
124392 | 
717 | 
0 | 
0 | 
| T146 | 
21400 | 
94 | 
0 | 
0 | 
| T147 | 
63943 | 
83 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
10641 | 
0 | 
0 | 
| T70 | 
66818 | 
1532 | 
0 | 
0 | 
| T101 | 
93985 | 
805 | 
0 | 
0 | 
| T103 | 
6387 | 
56 | 
0 | 
0 | 
| T105 | 
9304 | 
7 | 
0 | 
0 | 
| T106 | 
111689 | 
761 | 
0 | 
0 | 
| T132 | 
19576 | 
28 | 
0 | 
0 | 
| T133 | 
7227 | 
31 | 
0 | 
0 | 
| T145 | 
124392 | 
844 | 
0 | 
0 | 
| T146 | 
21400 | 
42 | 
0 | 
0 | 
| T147 | 
63943 | 
1038 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
11425 | 
0 | 
0 | 
| T70 | 
66818 | 
898 | 
0 | 
0 | 
| T101 | 
93985 | 
1361 | 
0 | 
0 | 
| T103 | 
6387 | 
10 | 
0 | 
0 | 
| T105 | 
9304 | 
97 | 
0 | 
0 | 
| T106 | 
111689 | 
743 | 
0 | 
0 | 
| T132 | 
19576 | 
27 | 
0 | 
0 | 
| T133 | 
7227 | 
12 | 
0 | 
0 | 
| T145 | 
124392 | 
886 | 
0 | 
0 | 
| T146 | 
21400 | 
75 | 
0 | 
0 | 
| T147 | 
63943 | 
1084 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
11713 | 
0 | 
0 | 
| T70 | 
66818 | 
1157 | 
0 | 
0 | 
| T101 | 
93985 | 
1490 | 
0 | 
0 | 
| T103 | 
6387 | 
74 | 
0 | 
0 | 
| T105 | 
9304 | 
92 | 
0 | 
0 | 
| T106 | 
111689 | 
747 | 
0 | 
0 | 
| T132 | 
19576 | 
60 | 
0 | 
0 | 
| T133 | 
7227 | 
14 | 
0 | 
0 | 
| T145 | 
124392 | 
758 | 
0 | 
0 | 
| T146 | 
21400 | 
52 | 
0 | 
0 | 
| T147 | 
63943 | 
1197 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
10801 | 
0 | 
0 | 
| T70 | 
66818 | 
1600 | 
0 | 
0 | 
| T101 | 
93985 | 
964 | 
0 | 
0 | 
| T103 | 
6387 | 
66 | 
0 | 
0 | 
| T105 | 
9304 | 
73 | 
0 | 
0 | 
| T106 | 
111689 | 
792 | 
0 | 
0 | 
| T132 | 
19576 | 
43 | 
0 | 
0 | 
| T133 | 
7227 | 
30 | 
0 | 
0 | 
| T145 | 
124392 | 
747 | 
0 | 
0 | 
| T146 | 
21400 | 
63 | 
0 | 
0 | 
| T147 | 
63943 | 
1099 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
11728 | 
0 | 
0 | 
| T70 | 
66818 | 
917 | 
0 | 
0 | 
| T101 | 
93985 | 
1006 | 
0 | 
0 | 
| T103 | 
6387 | 
148 | 
0 | 
0 | 
| T105 | 
9304 | 
72 | 
0 | 
0 | 
| T106 | 
111689 | 
777 | 
0 | 
0 | 
| T132 | 
19576 | 
35 | 
0 | 
0 | 
| T133 | 
7227 | 
30 | 
0 | 
0 | 
| T145 | 
124392 | 
817 | 
0 | 
0 | 
| T146 | 
21400 | 
60 | 
0 | 
0 | 
| T147 | 
63943 | 
1454 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
10413 | 
0 | 
0 | 
| T70 | 
66818 | 
1072 | 
0 | 
0 | 
| T101 | 
93985 | 
831 | 
0 | 
0 | 
| T103 | 
6387 | 
44 | 
0 | 
0 | 
| T105 | 
9304 | 
140 | 
0 | 
0 | 
| T106 | 
111689 | 
824 | 
0 | 
0 | 
| T132 | 
19576 | 
28 | 
0 | 
0 | 
| T133 | 
7227 | 
25 | 
0 | 
0 | 
| T145 | 
124392 | 
841 | 
0 | 
0 | 
| T146 | 
21400 | 
76 | 
0 | 
0 | 
| T147 | 
63943 | 
1346 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
10730 | 
0 | 
0 | 
| T70 | 
66818 | 
1070 | 
0 | 
0 | 
| T101 | 
93985 | 
1062 | 
0 | 
0 | 
| T103 | 
6387 | 
78 | 
0 | 
0 | 
| T105 | 
9304 | 
4 | 
0 | 
0 | 
| T106 | 
111689 | 
714 | 
0 | 
0 | 
| T132 | 
19576 | 
12 | 
0 | 
0 | 
| T133 | 
7227 | 
13 | 
0 | 
0 | 
| T145 | 
124392 | 
702 | 
0 | 
0 | 
| T146 | 
21400 | 
59 | 
0 | 
0 | 
| T147 | 
63943 | 
1285 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
11015 | 
0 | 
0 | 
| T70 | 
66818 | 
1515 | 
0 | 
0 | 
| T101 | 
93985 | 
877 | 
0 | 
0 | 
| T105 | 
9304 | 
81 | 
0 | 
0 | 
| T106 | 
111689 | 
705 | 
0 | 
0 | 
| T110 | 
7879 | 
219 | 
0 | 
0 | 
| T132 | 
19576 | 
42 | 
0 | 
0 | 
| T133 | 
7227 | 
44 | 
0 | 
0 | 
| T145 | 
124392 | 
701 | 
0 | 
0 | 
| T146 | 
21400 | 
71 | 
0 | 
0 | 
| T147 | 
63943 | 
1324 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6627 | 
0 | 
0 | 
| T70 | 
66818 | 
467 | 
0 | 
0 | 
| T101 | 
93985 | 
488 | 
0 | 
0 | 
| T103 | 
6387 | 
5 | 
0 | 
0 | 
| T105 | 
9304 | 
46 | 
0 | 
0 | 
| T106 | 
111689 | 
767 | 
0 | 
0 | 
| T132 | 
19576 | 
27 | 
0 | 
0 | 
| T133 | 
7227 | 
14 | 
0 | 
0 | 
| T145 | 
124392 | 
737 | 
0 | 
0 | 
| T146 | 
21400 | 
98 | 
0 | 
0 | 
| T147 | 
63943 | 
585 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6656 | 
0 | 
0 | 
| T70 | 
66818 | 
631 | 
0 | 
0 | 
| T101 | 
93985 | 
449 | 
0 | 
0 | 
| T103 | 
6387 | 
27 | 
0 | 
0 | 
| T105 | 
9304 | 
71 | 
0 | 
0 | 
| T106 | 
111689 | 
708 | 
0 | 
0 | 
| T132 | 
19576 | 
35 | 
0 | 
0 | 
| T133 | 
7227 | 
7 | 
0 | 
0 | 
| T145 | 
124392 | 
788 | 
0 | 
0 | 
| T146 | 
21400 | 
47 | 
0 | 
0 | 
| T147 | 
63943 | 
431 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
5796 | 
0 | 
0 | 
| T70 | 
66818 | 
534 | 
0 | 
0 | 
| T101 | 
93985 | 
350 | 
0 | 
0 | 
| T103 | 
6387 | 
21 | 
0 | 
0 | 
| T105 | 
9304 | 
40 | 
0 | 
0 | 
| T106 | 
111689 | 
704 | 
0 | 
0 | 
| T132 | 
19576 | 
24 | 
0 | 
0 | 
| T133 | 
7227 | 
23 | 
0 | 
0 | 
| T145 | 
124392 | 
807 | 
0 | 
0 | 
| T146 | 
21400 | 
50 | 
0 | 
0 | 
| T147 | 
63943 | 
347 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6752 | 
0 | 
0 | 
| T70 | 
66818 | 
647 | 
0 | 
0 | 
| T101 | 
93985 | 
542 | 
0 | 
0 | 
| T105 | 
9304 | 
2 | 
0 | 
0 | 
| T106 | 
111689 | 
745 | 
0 | 
0 | 
| T110 | 
7879 | 
36 | 
0 | 
0 | 
| T132 | 
19576 | 
52 | 
0 | 
0 | 
| T133 | 
7227 | 
3 | 
0 | 
0 | 
| T145 | 
124392 | 
790 | 
0 | 
0 | 
| T146 | 
21400 | 
70 | 
0 | 
0 | 
| T147 | 
63943 | 
480 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6283 | 
0 | 
0 | 
| T70 | 
66818 | 
534 | 
0 | 
0 | 
| T101 | 
93985 | 
504 | 
0 | 
0 | 
| T105 | 
9304 | 
34 | 
0 | 
0 | 
| T106 | 
111689 | 
758 | 
0 | 
0 | 
| T110 | 
7879 | 
97 | 
0 | 
0 | 
| T132 | 
19576 | 
50 | 
0 | 
0 | 
| T133 | 
7227 | 
2 | 
0 | 
0 | 
| T145 | 
124392 | 
866 | 
0 | 
0 | 
| T146 | 
21400 | 
62 | 
0 | 
0 | 
| T147 | 
63943 | 
347 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6018 | 
0 | 
0 | 
| T70 | 
66818 | 
633 | 
0 | 
0 | 
| T101 | 
93985 | 
267 | 
0 | 
0 | 
| T103 | 
6387 | 
21 | 
0 | 
0 | 
| T105 | 
9304 | 
62 | 
0 | 
0 | 
| T106 | 
111689 | 
720 | 
0 | 
0 | 
| T132 | 
19576 | 
50 | 
0 | 
0 | 
| T133 | 
7227 | 
28 | 
0 | 
0 | 
| T145 | 
124392 | 
809 | 
0 | 
0 | 
| T146 | 
21400 | 
56 | 
0 | 
0 | 
| T147 | 
63943 | 
487 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6817 | 
0 | 
0 | 
| T70 | 
66818 | 
512 | 
0 | 
0 | 
| T101 | 
93985 | 
569 | 
0 | 
0 | 
| T103 | 
6387 | 
27 | 
0 | 
0 | 
| T105 | 
9304 | 
29 | 
0 | 
0 | 
| T106 | 
111689 | 
789 | 
0 | 
0 | 
| T110 | 
7879 | 
59 | 
0 | 
0 | 
| T132 | 
19576 | 
21 | 
0 | 
0 | 
| T145 | 
124392 | 
772 | 
0 | 
0 | 
| T146 | 
21400 | 
92 | 
0 | 
0 | 
| T147 | 
63943 | 
462 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6755 | 
0 | 
0 | 
| T70 | 
66818 | 
591 | 
0 | 
0 | 
| T101 | 
93985 | 
569 | 
0 | 
0 | 
| T103 | 
6387 | 
30 | 
0 | 
0 | 
| T105 | 
9304 | 
15 | 
0 | 
0 | 
| T106 | 
111689 | 
672 | 
0 | 
0 | 
| T132 | 
19576 | 
21 | 
0 | 
0 | 
| T133 | 
7227 | 
18 | 
0 | 
0 | 
| T145 | 
124392 | 
765 | 
0 | 
0 | 
| T146 | 
21400 | 
45 | 
0 | 
0 | 
| T147 | 
63943 | 
617 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6017 | 
0 | 
0 | 
| T69 | 
18348 | 
2 | 
0 | 
0 | 
| T70 | 
66818 | 
557 | 
0 | 
0 | 
| T103 | 
6387 | 
26 | 
0 | 
0 | 
| T105 | 
9304 | 
45 | 
0 | 
0 | 
| T106 | 
111689 | 
745 | 
0 | 
0 | 
| T132 | 
19576 | 
41 | 
0 | 
0 | 
| T133 | 
7227 | 
12 | 
0 | 
0 | 
| T145 | 
124392 | 
812 | 
0 | 
0 | 
| T146 | 
21400 | 
76 | 
0 | 
0 | 
| T147 | 
63943 | 
541 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6552 | 
0 | 
0 | 
| T70 | 
66818 | 
594 | 
0 | 
0 | 
| T101 | 
93985 | 
426 | 
0 | 
0 | 
| T103 | 
6387 | 
48 | 
0 | 
0 | 
| T105 | 
9304 | 
36 | 
0 | 
0 | 
| T106 | 
111689 | 
809 | 
0 | 
0 | 
| T132 | 
19576 | 
19 | 
0 | 
0 | 
| T133 | 
7227 | 
20 | 
0 | 
0 | 
| T145 | 
124392 | 
779 | 
0 | 
0 | 
| T146 | 
21400 | 
86 | 
0 | 
0 | 
| T147 | 
63943 | 
561 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6031 | 
0 | 
0 | 
| T70 | 
66818 | 
492 | 
0 | 
0 | 
| T101 | 
93985 | 
530 | 
0 | 
0 | 
| T103 | 
6387 | 
76 | 
0 | 
0 | 
| T105 | 
9304 | 
1 | 
0 | 
0 | 
| T106 | 
111689 | 
767 | 
0 | 
0 | 
| T132 | 
19576 | 
18 | 
0 | 
0 | 
| T133 | 
7227 | 
28 | 
0 | 
0 | 
| T145 | 
124392 | 
738 | 
0 | 
0 | 
| T146 | 
21400 | 
11 | 
0 | 
0 | 
| T147 | 
63943 | 
302 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6328 | 
0 | 
0 | 
| T70 | 
66818 | 
563 | 
0 | 
0 | 
| T101 | 
93985 | 
483 | 
0 | 
0 | 
| T103 | 
6387 | 
12 | 
0 | 
0 | 
| T105 | 
9304 | 
55 | 
0 | 
0 | 
| T106 | 
111689 | 
745 | 
0 | 
0 | 
| T132 | 
19576 | 
30 | 
0 | 
0 | 
| T133 | 
7227 | 
31 | 
0 | 
0 | 
| T145 | 
124392 | 
762 | 
0 | 
0 | 
| T146 | 
21400 | 
61 | 
0 | 
0 | 
| T147 | 
63943 | 
418 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6458 | 
0 | 
0 | 
| T70 | 
66818 | 
464 | 
0 | 
0 | 
| T101 | 
93985 | 
430 | 
0 | 
0 | 
| T103 | 
6387 | 
59 | 
0 | 
0 | 
| T105 | 
9304 | 
56 | 
0 | 
0 | 
| T106 | 
111689 | 
822 | 
0 | 
0 | 
| T110 | 
7879 | 
98 | 
0 | 
0 | 
| T132 | 
19576 | 
36 | 
0 | 
0 | 
| T145 | 
124392 | 
782 | 
0 | 
0 | 
| T146 | 
21400 | 
40 | 
0 | 
0 | 
| T147 | 
63943 | 
636 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6522 | 
0 | 
0 | 
| T70 | 
66818 | 
488 | 
0 | 
0 | 
| T101 | 
93985 | 
295 | 
0 | 
0 | 
| T103 | 
6387 | 
4 | 
0 | 
0 | 
| T105 | 
9304 | 
10 | 
0 | 
0 | 
| T106 | 
111689 | 
850 | 
0 | 
0 | 
| T132 | 
19576 | 
28 | 
0 | 
0 | 
| T133 | 
7227 | 
53 | 
0 | 
0 | 
| T145 | 
124392 | 
819 | 
0 | 
0 | 
| T146 | 
21400 | 
66 | 
0 | 
0 | 
| T147 | 
63943 | 
395 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
7154 | 
0 | 
0 | 
| T70 | 
66818 | 
601 | 
0 | 
0 | 
| T101 | 
93985 | 
563 | 
0 | 
0 | 
| T103 | 
6387 | 
6 | 
0 | 
0 | 
| T105 | 
9304 | 
43 | 
0 | 
0 | 
| T106 | 
111689 | 
715 | 
0 | 
0 | 
| T132 | 
19576 | 
73 | 
0 | 
0 | 
| T133 | 
7227 | 
33 | 
0 | 
0 | 
| T145 | 
124392 | 
820 | 
0 | 
0 | 
| T146 | 
21400 | 
73 | 
0 | 
0 | 
| T147 | 
63943 | 
560 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
5823 | 
0 | 
0 | 
| T70 | 
66818 | 
655 | 
0 | 
0 | 
| T101 | 
93985 | 
281 | 
0 | 
0 | 
| T103 | 
6387 | 
51 | 
0 | 
0 | 
| T105 | 
9304 | 
23 | 
0 | 
0 | 
| T106 | 
111689 | 
820 | 
0 | 
0 | 
| T132 | 
19576 | 
54 | 
0 | 
0 | 
| T133 | 
7227 | 
8 | 
0 | 
0 | 
| T145 | 
124392 | 
677 | 
0 | 
0 | 
| T146 | 
21400 | 
51 | 
0 | 
0 | 
| T147 | 
63943 | 
366 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6447 | 
0 | 
0 | 
| T70 | 
66818 | 
524 | 
0 | 
0 | 
| T101 | 
93985 | 
551 | 
0 | 
0 | 
| T103 | 
6387 | 
7 | 
0 | 
0 | 
| T105 | 
9304 | 
30 | 
0 | 
0 | 
| T106 | 
111689 | 
738 | 
0 | 
0 | 
| T132 | 
19576 | 
40 | 
0 | 
0 | 
| T133 | 
7227 | 
49 | 
0 | 
0 | 
| T145 | 
124392 | 
821 | 
0 | 
0 | 
| T146 | 
21400 | 
91 | 
0 | 
0 | 
| T147 | 
63943 | 
459 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6245 | 
0 | 
0 | 
| T70 | 
66818 | 
516 | 
0 | 
0 | 
| T101 | 
93985 | 
398 | 
0 | 
0 | 
| T103 | 
6387 | 
30 | 
0 | 
0 | 
| T105 | 
9304 | 
39 | 
0 | 
0 | 
| T106 | 
111689 | 
791 | 
0 | 
0 | 
| T132 | 
19576 | 
25 | 
0 | 
0 | 
| T133 | 
7227 | 
37 | 
0 | 
0 | 
| T145 | 
124392 | 
831 | 
0 | 
0 | 
| T146 | 
21400 | 
71 | 
0 | 
0 | 
| T147 | 
63943 | 
549 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6233 | 
0 | 
0 | 
| T70 | 
66818 | 
488 | 
0 | 
0 | 
| T101 | 
93985 | 
553 | 
0 | 
0 | 
| T103 | 
6387 | 
6 | 
0 | 
0 | 
| T105 | 
9304 | 
37 | 
0 | 
0 | 
| T106 | 
111689 | 
749 | 
0 | 
0 | 
| T110 | 
7879 | 
54 | 
0 | 
0 | 
| T132 | 
19576 | 
66 | 
0 | 
0 | 
| T145 | 
124392 | 
785 | 
0 | 
0 | 
| T146 | 
21400 | 
107 | 
0 | 
0 | 
| T147 | 
63943 | 
379 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6289 | 
0 | 
0 | 
| T70 | 
66818 | 
415 | 
0 | 
0 | 
| T101 | 
93985 | 
517 | 
0 | 
0 | 
| T103 | 
6387 | 
19 | 
0 | 
0 | 
| T105 | 
9304 | 
78 | 
0 | 
0 | 
| T106 | 
111689 | 
742 | 
0 | 
0 | 
| T132 | 
19576 | 
38 | 
0 | 
0 | 
| T133 | 
7227 | 
13 | 
0 | 
0 | 
| T145 | 
124392 | 
760 | 
0 | 
0 | 
| T146 | 
21400 | 
65 | 
0 | 
0 | 
| T147 | 
63943 | 
477 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
5785 | 
0 | 
0 | 
| T70 | 
66818 | 
573 | 
0 | 
0 | 
| T101 | 
93985 | 
340 | 
0 | 
0 | 
| T103 | 
6387 | 
22 | 
0 | 
0 | 
| T105 | 
9304 | 
15 | 
0 | 
0 | 
| T106 | 
111689 | 
788 | 
0 | 
0 | 
| T132 | 
19576 | 
41 | 
0 | 
0 | 
| T133 | 
7227 | 
33 | 
0 | 
0 | 
| T145 | 
124392 | 
757 | 
0 | 
0 | 
| T146 | 
21400 | 
61 | 
0 | 
0 | 
| T147 | 
63943 | 
561 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6330 | 
0 | 
0 | 
| T70 | 
66818 | 
515 | 
0 | 
0 | 
| T101 | 
93985 | 
329 | 
0 | 
0 | 
| T103 | 
6387 | 
32 | 
0 | 
0 | 
| T105 | 
9304 | 
97 | 
0 | 
0 | 
| T106 | 
111689 | 
771 | 
0 | 
0 | 
| T132 | 
19576 | 
42 | 
0 | 
0 | 
| T133 | 
7227 | 
34 | 
0 | 
0 | 
| T145 | 
124392 | 
730 | 
0 | 
0 | 
| T146 | 
21400 | 
12 | 
0 | 
0 | 
| T147 | 
63943 | 
431 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6629 | 
0 | 
0 | 
| T70 | 
66818 | 
696 | 
0 | 
0 | 
| T101 | 
93985 | 
577 | 
0 | 
0 | 
| T103 | 
6387 | 
13 | 
0 | 
0 | 
| T105 | 
9304 | 
63 | 
0 | 
0 | 
| T106 | 
111689 | 
861 | 
0 | 
0 | 
| T132 | 
19576 | 
31 | 
0 | 
0 | 
| T133 | 
7227 | 
17 | 
0 | 
0 | 
| T145 | 
124392 | 
739 | 
0 | 
0 | 
| T146 | 
21400 | 
86 | 
0 | 
0 | 
| T147 | 
63943 | 
502 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
6059 | 
0 | 
0 | 
| T70 | 
66818 | 
639 | 
0 | 
0 | 
| T101 | 
93985 | 
459 | 
0 | 
0 | 
| T103 | 
6387 | 
7 | 
0 | 
0 | 
| T105 | 
9304 | 
39 | 
0 | 
0 | 
| T106 | 
111689 | 
687 | 
0 | 
0 | 
| T132 | 
19576 | 
18 | 
0 | 
0 | 
| T133 | 
7227 | 
26 | 
0 | 
0 | 
| T145 | 
124392 | 
785 | 
0 | 
0 | 
| T146 | 
21400 | 
70 | 
0 | 
0 | 
| T147 | 
63943 | 
422 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3522 | 
0 | 
0 | 
| T70 | 
66818 | 
102 | 
0 | 
0 | 
| T101 | 
93985 | 
122 | 
0 | 
0 | 
| T103 | 
6387 | 
1 | 
0 | 
0 | 
| T105 | 
9304 | 
7 | 
0 | 
0 | 
| T106 | 
111689 | 
720 | 
0 | 
0 | 
| T132 | 
19576 | 
38 | 
0 | 
0 | 
| T133 | 
7227 | 
15 | 
0 | 
0 | 
| T145 | 
124392 | 
763 | 
0 | 
0 | 
| T146 | 
21400 | 
57 | 
0 | 
0 | 
| T147 | 
63943 | 
100 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3768 | 
0 | 
0 | 
| T70 | 
66818 | 
121 | 
0 | 
0 | 
| T101 | 
93985 | 
50 | 
0 | 
0 | 
| T105 | 
9304 | 
3 | 
0 | 
0 | 
| T106 | 
111689 | 
798 | 
0 | 
0 | 
| T110 | 
7879 | 
29 | 
0 | 
0 | 
| T132 | 
19576 | 
32 | 
0 | 
0 | 
| T133 | 
7227 | 
20 | 
0 | 
0 | 
| T145 | 
124392 | 
806 | 
0 | 
0 | 
| T146 | 
21400 | 
61 | 
0 | 
0 | 
| T147 | 
63943 | 
86 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3650 | 
0 | 
0 | 
| T70 | 
66818 | 
145 | 
0 | 
0 | 
| T101 | 
93985 | 
78 | 
0 | 
0 | 
| T105 | 
9304 | 
4 | 
0 | 
0 | 
| T106 | 
111689 | 
709 | 
0 | 
0 | 
| T110 | 
7879 | 
22 | 
0 | 
0 | 
| T132 | 
19576 | 
44 | 
0 | 
0 | 
| T133 | 
7227 | 
6 | 
0 | 
0 | 
| T145 | 
124392 | 
807 | 
0 | 
0 | 
| T146 | 
21400 | 
65 | 
0 | 
0 | 
| T147 | 
63943 | 
138 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3804 | 
0 | 
0 | 
| T69 | 
18348 | 
5 | 
0 | 
0 | 
| T70 | 
66818 | 
100 | 
0 | 
0 | 
| T103 | 
6387 | 
1 | 
0 | 
0 | 
| T105 | 
9304 | 
8 | 
0 | 
0 | 
| T106 | 
111689 | 
751 | 
0 | 
0 | 
| T132 | 
19576 | 
58 | 
0 | 
0 | 
| T133 | 
7227 | 
28 | 
0 | 
0 | 
| T145 | 
124392 | 
804 | 
0 | 
0 | 
| T146 | 
21400 | 
83 | 
0 | 
0 | 
| T147 | 
63943 | 
115 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
4090 | 
0 | 
0 | 
| T70 | 
66818 | 
176 | 
0 | 
0 | 
| T101 | 
93985 | 
134 | 
0 | 
0 | 
| T103 | 
6387 | 
16 | 
0 | 
0 | 
| T105 | 
9304 | 
12 | 
0 | 
0 | 
| T106 | 
111689 | 
778 | 
0 | 
0 | 
| T132 | 
19576 | 
7 | 
0 | 
0 | 
| T133 | 
7227 | 
10 | 
0 | 
0 | 
| T145 | 
124392 | 
774 | 
0 | 
0 | 
| T146 | 
21400 | 
101 | 
0 | 
0 | 
| T147 | 
63943 | 
237 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
5896 | 
0 | 
0 | 
| T22 | 
528550 | 
20 | 
0 | 
0 | 
| T26 | 
36570 | 
0 | 
0 | 
0 | 
| T27 | 
873317 | 
0 | 
0 | 
0 | 
| T28 | 
0 | 
14 | 
0 | 
0 | 
| T129 | 
0 | 
92 | 
0 | 
0 | 
| T139 | 
407250 | 
0 | 
0 | 
0 | 
| T148 | 
0 | 
47 | 
0 | 
0 | 
| T149 | 
0 | 
22 | 
0 | 
0 | 
| T150 | 
0 | 
45 | 
0 | 
0 | 
| T151 | 
0 | 
42 | 
0 | 
0 | 
| T152 | 
0 | 
43 | 
0 | 
0 | 
| T153 | 
0 | 
21 | 
0 | 
0 | 
| T154 | 
0 | 
44 | 
0 | 
0 | 
| T155 | 
424513 | 
0 | 
0 | 
0 | 
| T156 | 
60656 | 
0 | 
0 | 
0 | 
| T157 | 
152945 | 
0 | 
0 | 
0 | 
| T158 | 
351187 | 
0 | 
0 | 
0 | 
| T159 | 
316542 | 
0 | 
0 | 
0 | 
| T160 | 
10540 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3916 | 
0 | 
0 | 
| T70 | 
66818 | 
116 | 
0 | 
0 | 
| T101 | 
93985 | 
69 | 
0 | 
0 | 
| T105 | 
9304 | 
10 | 
0 | 
0 | 
| T106 | 
111689 | 
809 | 
0 | 
0 | 
| T110 | 
7879 | 
11 | 
0 | 
0 | 
| T132 | 
19576 | 
56 | 
0 | 
0 | 
| T133 | 
7227 | 
41 | 
0 | 
0 | 
| T145 | 
124392 | 
847 | 
0 | 
0 | 
| T146 | 
21400 | 
135 | 
0 | 
0 | 
| T147 | 
63943 | 
126 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3821 | 
0 | 
0 | 
| T70 | 
66818 | 
112 | 
0 | 
0 | 
| T101 | 
93985 | 
135 | 
0 | 
0 | 
| T103 | 
6387 | 
9 | 
0 | 
0 | 
| T105 | 
9304 | 
6 | 
0 | 
0 | 
| T106 | 
111689 | 
797 | 
0 | 
0 | 
| T132 | 
19576 | 
44 | 
0 | 
0 | 
| T133 | 
7227 | 
36 | 
0 | 
0 | 
| T145 | 
124392 | 
738 | 
0 | 
0 | 
| T146 | 
21400 | 
75 | 
0 | 
0 | 
| T147 | 
63943 | 
133 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3521 | 
0 | 
0 | 
| T70 | 
66818 | 
95 | 
0 | 
0 | 
| T101 | 
93985 | 
70 | 
0 | 
0 | 
| T105 | 
9304 | 
9 | 
0 | 
0 | 
| T106 | 
111689 | 
821 | 
0 | 
0 | 
| T110 | 
7879 | 
8 | 
0 | 
0 | 
| T132 | 
19576 | 
56 | 
0 | 
0 | 
| T133 | 
7227 | 
4 | 
0 | 
0 | 
| T145 | 
124392 | 
721 | 
0 | 
0 | 
| T146 | 
21400 | 
49 | 
0 | 
0 | 
| T147 | 
63943 | 
69 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3397 | 
0 | 
0 | 
| T70 | 
66818 | 
74 | 
0 | 
0 | 
| T101 | 
93985 | 
43 | 
0 | 
0 | 
| T103 | 
6387 | 
13 | 
0 | 
0 | 
| T105 | 
9304 | 
17 | 
0 | 
0 | 
| T106 | 
111689 | 
770 | 
0 | 
0 | 
| T132 | 
19576 | 
40 | 
0 | 
0 | 
| T133 | 
7227 | 
20 | 
0 | 
0 | 
| T145 | 
124392 | 
744 | 
0 | 
0 | 
| T146 | 
21400 | 
55 | 
0 | 
0 | 
| T147 | 
63943 | 
76 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3522 | 
0 | 
0 | 
| T70 | 
66818 | 
91 | 
0 | 
0 | 
| T101 | 
93985 | 
44 | 
0 | 
0 | 
| T106 | 
111689 | 
773 | 
0 | 
0 | 
| T110 | 
7879 | 
4 | 
0 | 
0 | 
| T132 | 
19576 | 
43 | 
0 | 
0 | 
| T133 | 
7227 | 
15 | 
0 | 
0 | 
| T145 | 
124392 | 
819 | 
0 | 
0 | 
| T146 | 
21400 | 
104 | 
0 | 
0 | 
| T147 | 
63943 | 
87 | 
0 | 
0 | 
| T161 | 
11556 | 
53 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3235 | 
0 | 
0 | 
| T70 | 
66818 | 
85 | 
0 | 
0 | 
| T101 | 
93985 | 
51 | 
0 | 
0 | 
| T105 | 
9304 | 
17 | 
0 | 
0 | 
| T106 | 
111689 | 
742 | 
0 | 
0 | 
| T110 | 
7879 | 
4 | 
0 | 
0 | 
| T132 | 
19576 | 
26 | 
0 | 
0 | 
| T133 | 
7227 | 
28 | 
0 | 
0 | 
| T145 | 
124392 | 
738 | 
0 | 
0 | 
| T146 | 
21400 | 
36 | 
0 | 
0 | 
| T147 | 
63943 | 
57 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
4247 | 
0 | 
0 | 
| T70 | 
66818 | 
169 | 
0 | 
0 | 
| T101 | 
93985 | 
161 | 
0 | 
0 | 
| T103 | 
6387 | 
10 | 
0 | 
0 | 
| T105 | 
9304 | 
14 | 
0 | 
0 | 
| T106 | 
111689 | 
769 | 
0 | 
0 | 
| T132 | 
19576 | 
19 | 
0 | 
0 | 
| T133 | 
7227 | 
11 | 
0 | 
0 | 
| T145 | 
124392 | 
854 | 
0 | 
0 | 
| T146 | 
21400 | 
44 | 
0 | 
0 | 
| T147 | 
63943 | 
210 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3465 | 
0 | 
0 | 
| T70 | 
66818 | 
88 | 
0 | 
0 | 
| T101 | 
93985 | 
42 | 
0 | 
0 | 
| T105 | 
9304 | 
7 | 
0 | 
0 | 
| T106 | 
111689 | 
728 | 
0 | 
0 | 
| T110 | 
7879 | 
12 | 
0 | 
0 | 
| T132 | 
19576 | 
44 | 
0 | 
0 | 
| T133 | 
7227 | 
16 | 
0 | 
0 | 
| T145 | 
124392 | 
877 | 
0 | 
0 | 
| T146 | 
21400 | 
45 | 
0 | 
0 | 
| T147 | 
63943 | 
74 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
4227 | 
0 | 
0 | 
| T70 | 
66818 | 
220 | 
0 | 
0 | 
| T101 | 
93985 | 
181 | 
0 | 
0 | 
| T103 | 
6387 | 
13 | 
0 | 
0 | 
| T105 | 
9304 | 
9 | 
0 | 
0 | 
| T106 | 
111689 | 
773 | 
0 | 
0 | 
| T132 | 
19576 | 
37 | 
0 | 
0 | 
| T133 | 
7227 | 
29 | 
0 | 
0 | 
| T145 | 
124392 | 
753 | 
0 | 
0 | 
| T146 | 
21400 | 
73 | 
0 | 
0 | 
| T147 | 
63943 | 
216 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3879 | 
0 | 
0 | 
| T70 | 
66818 | 
135 | 
0 | 
0 | 
| T101 | 
93985 | 
111 | 
0 | 
0 | 
| T103 | 
6387 | 
4 | 
0 | 
0 | 
| T105 | 
9304 | 
3 | 
0 | 
0 | 
| T106 | 
111689 | 
725 | 
0 | 
0 | 
| T132 | 
19576 | 
57 | 
0 | 
0 | 
| T133 | 
7227 | 
34 | 
0 | 
0 | 
| T145 | 
124392 | 
811 | 
0 | 
0 | 
| T146 | 
21400 | 
118 | 
0 | 
0 | 
| T147 | 
63943 | 
159 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3327 | 
0 | 
0 | 
| T70 | 
66818 | 
71 | 
0 | 
0 | 
| T101 | 
93985 | 
50 | 
0 | 
0 | 
| T105 | 
9304 | 
9 | 
0 | 
0 | 
| T106 | 
111689 | 
736 | 
0 | 
0 | 
| T110 | 
7879 | 
7 | 
0 | 
0 | 
| T132 | 
19576 | 
31 | 
0 | 
0 | 
| T133 | 
7227 | 
23 | 
0 | 
0 | 
| T145 | 
124392 | 
812 | 
0 | 
0 | 
| T146 | 
21400 | 
68 | 
0 | 
0 | 
| T147 | 
63943 | 
56 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3407 | 
0 | 
0 | 
| T70 | 
66818 | 
45 | 
0 | 
0 | 
| T101 | 
93985 | 
45 | 
0 | 
0 | 
| T103 | 
6387 | 
5 | 
0 | 
0 | 
| T105 | 
9304 | 
14 | 
0 | 
0 | 
| T106 | 
111689 | 
753 | 
0 | 
0 | 
| T132 | 
19576 | 
28 | 
0 | 
0 | 
| T133 | 
7227 | 
17 | 
0 | 
0 | 
| T145 | 
124392 | 
815 | 
0 | 
0 | 
| T146 | 
21400 | 
91 | 
0 | 
0 | 
| T147 | 
63943 | 
92 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3522 | 
0 | 
0 | 
| T70 | 
66818 | 
58 | 
0 | 
0 | 
| T101 | 
93985 | 
52 | 
0 | 
0 | 
| T103 | 
6387 | 
10 | 
0 | 
0 | 
| T105 | 
9304 | 
10 | 
0 | 
0 | 
| T106 | 
111689 | 
758 | 
0 | 
0 | 
| T132 | 
19576 | 
21 | 
0 | 
0 | 
| T133 | 
7227 | 
10 | 
0 | 
0 | 
| T145 | 
124392 | 
786 | 
0 | 
0 | 
| T146 | 
21400 | 
67 | 
0 | 
0 | 
| T147 | 
63943 | 
78 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3438 | 
0 | 
0 | 
| T70 | 
66818 | 
70 | 
0 | 
0 | 
| T101 | 
93985 | 
53 | 
0 | 
0 | 
| T103 | 
6387 | 
1 | 
0 | 
0 | 
| T105 | 
9304 | 
10 | 
0 | 
0 | 
| T106 | 
111689 | 
742 | 
0 | 
0 | 
| T132 | 
19576 | 
74 | 
0 | 
0 | 
| T133 | 
7227 | 
5 | 
0 | 
0 | 
| T145 | 
124392 | 
760 | 
0 | 
0 | 
| T146 | 
21400 | 
47 | 
0 | 
0 | 
| T147 | 
63943 | 
84 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3319 | 
0 | 
0 | 
| T70 | 
66818 | 
91 | 
0 | 
0 | 
| T101 | 
93985 | 
40 | 
0 | 
0 | 
| T103 | 
6387 | 
4 | 
0 | 
0 | 
| T105 | 
9304 | 
4 | 
0 | 
0 | 
| T106 | 
111689 | 
748 | 
0 | 
0 | 
| T132 | 
19576 | 
48 | 
0 | 
0 | 
| T133 | 
7227 | 
26 | 
0 | 
0 | 
| T145 | 
124392 | 
727 | 
0 | 
0 | 
| T146 | 
21400 | 
64 | 
0 | 
0 | 
| T147 | 
63943 | 
86 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
439684255 | 
3239 | 
0 | 
0 | 
| T70 | 
66818 | 
65 | 
0 | 
0 | 
| T101 | 
93985 | 
75 | 
0 | 
0 | 
| T103 | 
6387 | 
2 | 
0 | 
0 | 
| T106 | 
111689 | 
794 | 
0 | 
0 | 
| T110 | 
7879 | 
6 | 
0 | 
0 | 
| T132 | 
19576 | 
39 | 
0 | 
0 | 
| T133 | 
7227 | 
27 | 
0 | 
0 | 
| T145 | 
124392 | 
732 | 
0 | 
0 | 
| T146 | 
21400 | 
73 | 
0 | 
0 | 
| T147 | 
63943 | 
72 | 
0 | 
0 |