Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4108818	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4472544

1

T1

1032

T2

11174

T3

18227

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4779096	1			T1	231		T2	1410		T3	8058
values[0x0]	1899987	1			T1	443		T2	5221		T3	8660
values[0x1]	1902279	1			T1	467		T2	5313		T3	9041

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2896551	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5684811

1

T1

1054

T2

11349

T3

20319

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	35087	1			T2	58		T3	101		T5	4
valid_sources[0x01]	34564	1			T2	41		T3	97		T5	9
valid_sources[0x02]	33353	1			T2	57		T3	99		T5	17
valid_sources[0x03]	30872	1			T2	49		T3	98		T5	5
valid_sources[0x04]	31680	1			T2	49		T3	108		T5	4
valid_sources[0x05]	30948	1			T2	45		T3	121		T5	1
valid_sources[0x06]	28781	1			T2	65		T3	105		T5	5
valid_sources[0x07]	33276	1			T2	41		T3	141		T5	12
valid_sources[0x08]	32265	1			T2	34		T3	72		T4	84
valid_sources[0x09]	35799	1			T2	45		T3	91		T6	42
valid_sources[0x0a]	31093	1			T2	37		T3	95		T5	12
valid_sources[0x0b]	30863	1			T1	476		T2	51		T3	94
valid_sources[0x0c]	32954	1			T2	48		T3	99		T5	5
valid_sources[0x0d]	32926	1			T2	48		T3	82		T5	9
valid_sources[0x0e]	32566	1			T2	72		T3	108		T5	23
valid_sources[0x0f]	32604	1			T2	56		T3	100		T5	1
valid_sources[0x10]	31305	1			T2	44		T3	122		T5	2
valid_sources[0x11]	34723	1			T2	53		T3	105		T6	43
valid_sources[0x12]	33095	1			T2	49		T3	111		T5	1
valid_sources[0x13]	31221	1			T2	65		T3	116		T5	11
valid_sources[0x14]	39375	1			T2	46		T3	89		T5	9
valid_sources[0x15]	31589	1			T2	30		T3	100		T5	27
valid_sources[0x16]	32465	1			T2	41		T3	90		T5	4
valid_sources[0x17]	30981	1			T2	54		T3	93		T5	28
valid_sources[0x18]	32900	1			T2	53		T3	125		T5	16
valid_sources[0x19]	32938	1			T2	51		T3	95		T5	17
valid_sources[0x1a]	33612	1			T2	55		T3	108		T5	11
valid_sources[0x1b]	32713	1			T2	42		T3	129		T5	5
valid_sources[0x1c]	32450	1			T2	53		T3	89		T5	2
valid_sources[0x1d]	36322	1			T2	46		T3	106		T5	10
valid_sources[0x1e]	30688	1			T2	48		T3	91		T5	5
valid_sources[0x1f]	32935	1			T2	67		T3	109		T4	118
valid_sources[0x20]	35628	1			T2	39		T3	114		T5	7
valid_sources[0x21]	32990	1			T2	51		T3	101		T5	12
valid_sources[0x22]	35217	1			T2	50		T3	85		T5	16
valid_sources[0x23]	32717	1			T2	49		T3	92		T5	10
valid_sources[0x24]	34566	1			T2	50		T3	107		T6	43
valid_sources[0x25]	32690	1			T2	45		T3	103		T5	4
valid_sources[0x26]	32953	1			T2	65		T3	93		T5	3
valid_sources[0x27]	35672	1			T2	33		T3	84		T5	10
valid_sources[0x28]	33539	1			T2	38		T3	102		T5	25
valid_sources[0x29]	31597	1			T2	73		T3	130		T5	17
valid_sources[0x2a]	31224	1			T2	31		T3	86		T5	14
valid_sources[0x2b]	34530	1			T2	47		T3	100		T5	12
valid_sources[0x2c]	31632	1			T2	38		T3	119		T5	4
valid_sources[0x2d]	34118	1			T2	65		T3	85		T5	12
valid_sources[0x2e]	32341	1			T2	59		T3	114		T6	48
valid_sources[0x2f]	31281	1			T2	47		T3	103		T5	8
valid_sources[0x30]	32077	1			T2	44		T3	99		T5	4
valid_sources[0x31]	35860	1			T2	37		T3	87		T5	25
valid_sources[0x32]	32552	1			T2	35		T3	68		T6	55
valid_sources[0x33]	31808	1			T2	55		T3	91		T5	12
valid_sources[0x34]	35148	1			T2	58		T3	87		T6	52
valid_sources[0x35]	31104	1			T2	56		T3	103		T5	5
valid_sources[0x36]	29099	1			T2	52		T3	90		T5	12
valid_sources[0x37]	33902	1			T2	37		T3	99		T5	13
valid_sources[0x38]	34504	1			T2	35		T3	102		T5	21
valid_sources[0x39]	32716	1			T2	43		T3	98		T5	8
valid_sources[0x3a]	33118	1			T2	65		T3	98		T5	14
valid_sources[0x3b]	31485	1			T2	51		T3	117		T5	5
valid_sources[0x3c]	31627	1			T2	40		T3	110		T5	8
valid_sources[0x3d]	37111	1			T2	60		T3	77		T5	8
valid_sources[0x3e]	30580	1			T2	43		T3	102		T5	2
valid_sources[0x3f]	31976	1			T2	44		T3	113		T5	11
valid_sources[0x40]	31397	1			T2	45		T3	107		T5	9
valid_sources[0x41]	30888	1			T2	30		T3	114		T5	13
valid_sources[0x42]	39405	1			T2	46		T3	107		T5	6
valid_sources[0x43]	30725	1			T2	53		T3	97		T5	14
valid_sources[0x44]	32431	1			T2	50		T3	97		T5	14
valid_sources[0x45]	31437	1			T2	40		T3	116		T5	8
valid_sources[0x46]	31804	1			T2	51		T3	88		T5	5
valid_sources[0x47]	32363	1			T2	51		T3	88		T5	5
valid_sources[0x48]	30793	1			T2	27		T3	92		T5	7
valid_sources[0x49]	41060	1			T2	40		T3	104		T5	13
valid_sources[0x4a]	34364	1			T2	72		T3	106		T5	4
valid_sources[0x4b]	32160	1			T2	37		T3	96		T5	4
valid_sources[0x4c]	32051	1			T2	28		T3	91		T5	12
valid_sources[0x4d]	37868	1			T2	57		T3	105		T5	4
valid_sources[0x4e]	34854	1			T2	44		T3	79		T5	4
valid_sources[0x4f]	32302	1			T2	25		T3	86		T5	9
valid_sources[0x50]	40306	1			T2	36		T3	90		T5	14
valid_sources[0x51]	36194	1			T2	63		T3	93		T5	1
valid_sources[0x52]	32788	1			T2	36		T3	101		T6	51
valid_sources[0x53]	31190	1			T2	43		T3	69		T5	8
valid_sources[0x54]	32360	1			T2	58		T3	113		T5	4
valid_sources[0x55]	32539	1			T2	50		T3	90		T5	34
valid_sources[0x56]	30439	1			T2	55		T3	103		T5	6
valid_sources[0x57]	30193	1			T2	52		T3	88		T5	6
valid_sources[0x58]	31641	1			T2	50		T3	98		T5	6
valid_sources[0x59]	45131	1			T2	62		T3	103		T5	5
valid_sources[0x5a]	37873	1			T2	51		T3	120		T5	9
valid_sources[0x5b]	32948	1			T2	37		T3	114		T5	1
valid_sources[0x5c]	38009	1			T2	33		T3	90		T5	9
valid_sources[0x5d]	34063	1			T2	41		T3	102		T5	13
valid_sources[0x5e]	32095	1			T2	39		T3	97		T5	11
valid_sources[0x5f]	33674	1			T2	34		T3	81		T5	14
valid_sources[0x60]	32307	1			T2	60		T3	113		T5	8
valid_sources[0x61]	31184	1			T2	49		T3	92		T5	2
valid_sources[0x62]	31622	1			T2	46		T3	98		T5	27
valid_sources[0x63]	33001	1			T2	33		T3	112		T6	52
valid_sources[0x64]	33862	1			T2	45		T3	97		T5	2
valid_sources[0x65]	34189	1			T2	69		T3	85		T5	7
valid_sources[0x66]	31392	1			T2	54		T3	111		T5	16
valid_sources[0x67]	31395	1			T2	57		T3	109		T5	8
valid_sources[0x68]	38536	1			T2	37		T3	92		T5	23
valid_sources[0x69]	36700	1			T2	52		T3	127		T5	12
valid_sources[0x6a]	32025	1			T2	46		T3	107		T5	6
valid_sources[0x6b]	38368	1			T2	45		T3	83		T5	21
valid_sources[0x6c]	29654	1			T2	55		T3	86		T5	2
valid_sources[0x6d]	34396	1			T2	36		T3	101		T5	12
valid_sources[0x6e]	34277	1			T2	51		T3	123		T5	8
valid_sources[0x6f]	32732	1			T1	54		T2	28		T3	109
valid_sources[0x70]	31538	1			T2	35		T3	105		T5	14
valid_sources[0x71]	58331	1			T2	41		T3	86		T6	48
valid_sources[0x72]	30133	1			T2	50		T3	100		T5	4
valid_sources[0x73]	38058	1			T2	53		T3	84		T5	37
valid_sources[0x74]	32192	1			T2	53		T3	113		T5	3
valid_sources[0x75]	32172	1			T2	50		T3	130		T5	10
valid_sources[0x76]	32470	1			T2	60		T3	92		T5	10
valid_sources[0x77]	42188	1			T2	50		T3	110		T5	5
valid_sources[0x78]	31989	1			T2	50		T3	89		T5	13
valid_sources[0x79]	33812	1			T2	40		T3	96		T4	1451
valid_sources[0x7a]	33954	1			T2	50		T3	96		T5	12
valid_sources[0x7b]	33734	1			T2	53		T3	84		T6	48
valid_sources[0x7c]	45675	1			T2	48		T3	111		T5	13
valid_sources[0x7d]	34020	1			T2	41		T3	65		T5	6
valid_sources[0x7e]	31352	1			T2	56		T3	73		T5	19
valid_sources[0x7f]	36039	1			T2	33		T3	94		T5	8
valid_sources[0x80]	33074	1			T2	44		T3	99		T5	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1050334

1

T1

129

T2

680

T3

1988

values[0x0]

all_enables

biggest_size

1724110

1

T1

440

T2

5210

T3

8036

values[0x1]

all_enables

biggest_size

1698100

1

T1

463

T2

5284

T3

8203