Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4133282

1

T1

109

T2

770

T3

7532

full_word

4474009

1

T1

1032

T2

11174

T3

18227

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8606861	1			T1	1141		T2	11944		T3	25759
auto[TlIntgErrCmd]	145	1			T53	6		T85	4		T86	8
auto[TlIntgErrData]	138	1			T53	8		T85	3		T86	7
auto[TlIntgErrBoth]	147	1			T53	6		T85	3		T86	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4783827

1

T1

231

T2

1410

T3

8058

auto[1]

3823464

1

T1

910

T2

10534

T3

17701

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3732948	1			T1	102		T2	730		T3	6070
auto[TlIntgErrNone]	partial	auto[1]	399937	1			T1	7		T2	40		T3	1462
auto[TlIntgErrNone]	full_word	auto[0]	1050695	1			T1	129		T2	680		T3	1988
auto[TlIntgErrNone]	full_word	auto[1]	3423281	1			T1	903		T2	10494		T3	16239
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T53	2		T85	2		T86	3
auto[TlIntgErrCmd]	partial	auto[1]	86	1			T53	3		T85	2		T86	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T53	1		T156	1		T157	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T141	3		T152	1		T160	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T53	5		T85	1		T86	2
auto[TlIntgErrData]	partial	auto[1]	59	1			T53	3		T85	1		T86	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T85	1		T86	2		T161	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T162	2		T157	1		T163	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T53	2		T85	2		T86	2
auto[TlIntgErrBoth]	partial	auto[1]	86	1			T53	3		T86	3		T137	4
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T53	1		T85	1		T137	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T137	1		T141	1		T164	1