Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	650017888	3446994	0	0
gen_wmask[1].MaskCheckPortA_A	650017888	3446994	0	0
gen_wmask[2].MaskCheckPortA_A	650017888	3446994	0	0
gen_wmask[3].MaskCheckPortA_A	650017888	3446994	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650017888	3446994	0	0
T1	14199	832	0	0
T2	1015653	10248	0	0
T3	711658	27351	0	0
T4	171252	832	0	0
T5	127560	1602	0	0
T6	1893903	13521	0	0
T7	410373	832	0	0
T8	728668	4692	0	0
T9	18571	832	0	0
T10	6096	82	0	0
T11	205455	22354	0	0
T23	0	4	0	0
T24	0	9064	0	0
T26	0	1748	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650017888	3446994	0	0
T1	14199	832	0	0
T2	1015653	10248	0	0
T3	711658	27351	0	0
T4	171252	832	0	0
T5	127560	1602	0	0
T6	1893903	13521	0	0
T7	410373	832	0	0
T8	728668	4692	0	0
T9	18571	832	0	0
T10	6096	82	0	0
T11	205455	22354	0	0
T23	0	4	0	0
T24	0	9064	0	0
T26	0	1748	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650017888	3446994	0	0
T1	14199	832	0	0
T2	1015653	10248	0	0
T3	711658	27351	0	0
T4	171252	832	0	0
T5	127560	1602	0	0
T6	1893903	13521	0	0
T7	410373	832	0	0
T8	728668	4692	0	0
T9	18571	832	0	0
T10	6096	82	0	0
T11	205455	22354	0	0
T23	0	4	0	0
T24	0	9064	0	0
T26	0	1748	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650017888	3446994	0	0
T1	14199	832	0	0
T2	1015653	10248	0	0
T3	711658	27351	0	0
T4	171252	832	0	0
T5	127560	1602	0	0
T6	1893903	13521	0	0
T7	410373	832	0	0
T8	728668	4692	0	0
T9	18571	832	0	0
T10	6096	82	0	0
T11	205455	22354	0	0
T23	0	4	0	0
T24	0	9064	0	0
T26	0	1748	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	498030239	2114247	0	0
gen_wmask[1].MaskCheckPortA_A	498030239	2114247	0	0
gen_wmask[2].MaskCheckPortA_A	498030239	2114247	0	0
gen_wmask[3].MaskCheckPortA_A	498030239	2114247	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	2114247	0	0
T1	14199	832	0	0
T2	555741	9984	0	0
T3	557095	13179	0	0
T4	150769	832	0	0
T5	67033	363	0	0
T6	977511	9984	0	0
T7	210987	832	0	0
T8	380380	4160	0	0
T9	7081	832	0	0
T10	3691	34	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	2114247	0	0
T1	14199	832	0	0
T2	555741	9984	0	0
T3	557095	13179	0	0
T4	150769	832	0	0
T5	67033	363	0	0
T6	977511	9984	0	0
T7	210987	832	0	0
T8	380380	4160	0	0
T9	7081	832	0	0
T10	3691	34	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	2114247	0	0
T1	14199	832	0	0
T2	555741	9984	0	0
T3	557095	13179	0	0
T4	150769	832	0	0
T5	67033	363	0	0
T6	977511	9984	0	0
T7	210987	832	0	0
T8	380380	4160	0	0
T9	7081	832	0	0
T10	3691	34	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	2114247	0	0
T1	14199	832	0	0
T2	555741	9984	0	0
T3	557095	13179	0	0
T4	150769	832	0	0
T5	67033	363	0	0
T6	977511	9984	0	0
T7	210987	832	0	0
T8	380380	4160	0	0
T9	7081	832	0	0
T10	3691	34	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	151987649	1332747	0	0
gen_wmask[1].MaskCheckPortA_A	151987649	1332747	0	0
gen_wmask[2].MaskCheckPortA_A	151987649	1332747	0	0
gen_wmask[3].MaskCheckPortA_A	151987649	1332747	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	1332747	0	0
T2	459912	264	0	0
T3	154563	14172	0	0
T4	20483	0	0	0
T5	60527	1239	0	0
T6	916392	3537	0	0
T7	199386	0	0	0
T8	348288	532	0	0
T9	11490	0	0	0
T10	2405	48	0	0
T11	205455	22354	0	0
T23	0	4	0	0
T24	0	9064	0	0
T26	0	1748	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	1332747	0	0
T2	459912	264	0	0
T3	154563	14172	0	0
T4	20483	0	0	0
T5	60527	1239	0	0
T6	916392	3537	0	0
T7	199386	0	0	0
T8	348288	532	0	0
T9	11490	0	0	0
T10	2405	48	0	0
T11	205455	22354	0	0
T23	0	4	0	0
T24	0	9064	0	0
T26	0	1748	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	1332747	0	0
T2	459912	264	0	0
T3	154563	14172	0	0
T4	20483	0	0	0
T5	60527	1239	0	0
T6	916392	3537	0	0
T7	199386	0	0	0
T8	348288	532	0	0
T9	11490	0	0	0
T10	2405	48	0	0
T11	205455	22354	0	0
T23	0	4	0	0
T24	0	9064	0	0
T26	0	1748	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	1332747	0	0
T2	459912	264	0	0
T3	154563	14172	0	0
T4	20483	0	0	0
T5	60527	1239	0	0
T6	916392	3537	0	0
T7	199386	0	0	0
T8	348288	532	0	0
T9	11490	0	0	0
T10	2405	48	0	0
T11	205455	22354	0	0
T23	0	4	0	0
T24	0	9064	0	0
T26	0	1748	0	0