Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500315288	2904498	0	0
DepthKnown_A	500315288	500181252	0	0
RvalidKnown_A	500315288	500181252	0	0
WreadyKnown_A	500315288	500181252	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	2904498	0	0
T1	14199	1665	0	0
T2	555741	14143	0	0
T3	557095	17465	0	0
T4	150769	832	0	0
T5	67033	0	0	0
T6	977511	17463	0	0
T7	210987	832	0	0
T8	380380	5822	0	0
T9	7081	1663	0	0
T10	3691	0	0	0
T11	0	29940	0	0
T22	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500315288	3104741	0	0
DepthKnown_A	500315288	500181252	0	0
RvalidKnown_A	500315288	500181252	0	0
WreadyKnown_A	500315288	500181252	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	3104741	0	0
T1	14199	834	0	0
T2	555741	21862	0	0
T3	557095	11648	0	0
T4	150769	832	0	0
T5	67033	0	0	0
T6	977511	9984	0	0
T7	210987	832	0	0
T8	380380	4160	0	0
T9	7081	832	0	0
T10	3691	0	0	0
T11	0	19968	0	0
T22	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500315288	198657	0	0
DepthKnown_A	500315288	500181252	0	0
RvalidKnown_A	500315288	500181252	0	0
WreadyKnown_A	500315288	500181252	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	198657	0	0
T2	555741	64	0	0
T3	557095	1306	0	0
T4	150769	0	0	0
T5	67033	319	0	0
T6	977511	295	0	0
T7	210987	0	0	0
T8	380380	65	0	0
T9	7081	0	0	0
T10	3691	14	0	0
T11	0	2327	0	0
T22	3346	0	0	0
T23	0	1	0	0
T24	0	1017	0	0
T26	0	310	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500315288	419028	0	0
DepthKnown_A	500315288	500181252	0	0
RvalidKnown_A	500315288	500181252	0	0
WreadyKnown_A	500315288	500181252	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	419028	0	0
T2	555741	220	0	0
T3	557095	1303	0	0
T4	150769	0	0	0
T5	67033	319	0	0
T6	977511	295	0	0
T7	210987	0	0	0
T8	380380	65	0	0
T9	7081	0	0	0
T10	3691	79	0	0
T11	0	2326	0	0
T22	3346	0	0	0
T23	0	1	0	0
T24	0	1013	0	0
T26	0	309	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500315288	6937907	0	0
DepthKnown_A	500315288	500181252	0	0
RvalidKnown_A	500315288	500181252	0	0
WreadyKnown_A	500315288	500181252	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	6937907	0	0
T1	14199	316	0	0
T2	555741	1910	0	0
T3	557095	13025	0	0
T4	150769	2108	0	0
T5	67033	1936	0	0
T6	977511	2491	0	0
T7	210987	9474	0	0
T8	380380	912	0	0
T9	7081	161	0	0
T10	3691	141	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500315288	13944757	0	0
DepthKnown_A	500315288	500181252	0	0
RvalidKnown_A	500315288	500181252	0	0
WreadyKnown_A	500315288	500181252	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	13944757	0	0
T1	14199	1427	0	0
T2	555741	5885	0	0
T3	557095	12808	0	0
T4	150769	2107	0	0
T5	67033	1930	0	0
T6	977511	2487	0	0
T7	210987	9474	0	0
T8	380380	912	0	0
T9	7081	161	0	0
T10	3691	617	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500315288	500181252	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0