Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T10
1	0	Covered	T3,T5,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T10
1	0	Unreachable
1	1	Covered	T3,T5,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	802005537	648549743	0	0
CheckNGreaterZero_A	2865	2865	0	0
GntImpliesReady_A	802005537	3853436	0	0
GntImpliesValid_A	802005537	3853436	0	0
GrantKnown_A	802005537	648549743	0	0
IdxKnown_A	802005537	648549743	0	0
IndexIsCorrect_A	802005537	3853436	0	0
LockArbDecision_A	802005537	0	0	0
NoReadyValidNoGrant_A	802005537	0	0	0
ReadyAndValidImplyGrant_A	802005537	3853436	0	0
ReqAndReadyImplyGrant_A	802005537	3853436	0	0
ReqImpliesValid_A	802005537	3853436	0	0
ReqStaysHighUntilGranted0_M	802005537	0	0	0
RoundRobin_A	802005537	5	0	955
ValidKnown_A	802005537	648549743	0	0
gen_data_port_assertion.DataFlow_A	802005537	3853436	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802005537	648549743	0	0
T1	55607	55533	0	0
T2	1015653	1013420	0	0
T3	866221	1096063	0	0
T4	191735	171197	0	0
T5	188087	124921	0	0
T6	2810295	1890148	0	0
T7	609759	409402	0	0
T8	1076956	727584	0	0
T9	30061	18480	0	0
T10	8501	5936	0	0
T11	205455	395929	0	0
T13	181152	181152	0	0
T14	0	288	0	0
T23	0	424	0	0
T24	0	380088	0	0
T25	0	360	0	0
T26	0	87040	0	0
T27	0	248	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2865	2865	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802005537	3853436	0	0
T1	14199	832	0	0
T2	1015653	10318	0	0
T3	866221	30369	0	0
T4	191735	832	0	0
T5	188087	2320	0	0
T6	2810295	13836	0	0
T7	609759	832	0	0
T8	1076956	4772	0	0
T9	30061	832	0	0
T10	8501	133	0	0
T11	410910	25209	0	0
T13	181152	0	0	0
T23	0	8	0	0
T24	0	10614	0	0
T26	0	2153	0	0
T27	0	5	0	0
T30	0	2410	0	0
T31	0	5546	0	0
T40	0	100	0	0
T41	0	3890	0	0
T42	0	3647	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802005537	3853436	0	0
T1	14199	832	0	0
T2	1015653	10318	0	0
T3	866221	30369	0	0
T4	191735	832	0	0
T5	188087	2320	0	0
T6	2810295	13836	0	0
T7	609759	832	0	0
T8	1076956	4772	0	0
T9	30061	832	0	0
T10	8501	133	0	0
T11	410910	25209	0	0
T13	181152	0	0	0
T23	0	8	0	0
T24	0	10614	0	0
T26	0	2153	0	0
T27	0	5	0	0
T30	0	2410	0	0
T31	0	5546	0	0
T40	0	100	0	0
T41	0	3890	0	0
T42	0	3647	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802005537	648549743	0	0
T1	55607	55533	0	0
T2	1015653	1013420	0	0
T3	866221	1096063	0	0
T4	191735	171197	0	0
T5	188087	124921	0	0
T6	2810295	1890148	0	0
T7	609759	409402	0	0
T8	1076956	727584	0	0
T9	30061	18480	0	0
T10	8501	5936	0	0
T11	205455	395929	0	0
T13	181152	181152	0	0
T14	0	288	0	0
T23	0	424	0	0
T24	0	380088	0	0
T25	0	360	0	0
T26	0	87040	0	0
T27	0	248	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802005537	648549743	0	0
T1	55607	55533	0	0
T2	1015653	1013420	0	0
T3	866221	1096063	0	0
T4	191735	171197	0	0
T5	188087	124921	0	0
T6	2810295	1890148	0	0
T7	609759	409402	0	0
T8	1076956	727584	0	0
T9	30061	18480	0	0
T10	8501	5936	0	0
T11	205455	395929	0	0
T13	181152	181152	0	0
T14	0	288	0	0
T23	0	424	0	0
T24	0	380088	0	0
T25	0	360	0	0
T26	0	87040	0	0
T27	0	248	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802005537	3853436	0	0
T1	14199	832	0	0
T2	1015653	10318	0	0
T3	866221	30369	0	0
T4	191735	832	0	0
T5	188087	2320	0	0
T6	2810295	13836	0	0
T7	609759	832	0	0
T8	1076956	4772	0	0
T9	30061	832	0	0
T10	8501	133	0	0
T11	410910	25209	0	0
T13	181152	0	0	0
T23	0	8	0	0
T24	0	10614	0	0
T26	0	2153	0	0
T27	0	5	0	0
T30	0	2410	0	0
T31	0	5546	0	0
T40	0	100	0	0
T41	0	3890	0	0
T42	0	3647	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802005537	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802005537	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802005537	3853436	0	0
T1	14199	832	0	0
T2	1015653	10318	0	0
T3	866221	30369	0	0
T4	191735	832	0	0
T5	188087	2320	0	0
T6	2810295	13836	0	0
T7	609759	832	0	0
T8	1076956	4772	0	0
T9	30061	832	0	0
T10	8501	133	0	0
T11	410910	25209	0	0
T13	181152	0	0	0
T23	0	8	0	0
T24	0	10614	0	0
T26	0	2153	0	0
T27	0	5	0	0
T30	0	2410	0	0
T31	0	5546	0	0
T40	0	100	0	0
T41	0	3890	0	0
T42	0	3647	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802005537	3853436	0	0
T1	14199	832	0	0
T2	1015653	10318	0	0
T3	866221	30369	0	0
T4	191735	832	0	0
T5	188087	2320	0	0
T6	2810295	13836	0	0
T7	609759	832	0	0
T8	1076956	4772	0	0
T9	30061	832	0	0
T10	8501	133	0	0
T11	410910	25209	0	0
T13	181152	0	0	0
T23	0	8	0	0
T24	0	10614	0	0
T26	0	2153	0	0
T27	0	5	0	0
T30	0	2410	0	0
T31	0	5546	0	0
T40	0	100	0	0
T41	0	3890	0	0
T42	0	3647	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802005537	3853436	0	0
T1	14199	832	0	0
T2	1015653	10318	0	0
T3	866221	30369	0	0
T4	191735	832	0	0
T5	188087	2320	0	0
T6	2810295	13836	0	0
T7	609759	832	0	0
T8	1076956	4772	0	0
T9	30061	832	0	0
T10	8501	133	0	0
T11	410910	25209	0	0
T13	181152	0	0	0
T23	0	8	0	0
T24	0	10614	0	0
T26	0	2153	0	0
T27	0	5	0	0
T30	0	2410	0	0
T31	0	5546	0	0
T40	0	100	0	0
T41	0	3890	0	0
T42	0	3647	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	802005537	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802005537	5	0	955
T24	239141	1	0	1
T25	3342	0	0	1
T26	81095	0	0	1
T27	974	0	0	1
T28	230302	0	0	1
T30	182507	0	0	1
T32	137188	0	0	1
T42	144267	0	0	1
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	1252	0	0	1
T48	281185	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802005537	648549743	0	0
T1	55607	55533	0	0
T2	1015653	1013420	0	0
T3	866221	1096063	0	0
T4	191735	171197	0	0
T5	188087	124921	0	0
T6	2810295	1890148	0	0
T7	609759	409402	0	0
T8	1076956	727584	0	0
T9	30061	18480	0	0
T10	8501	5936	0	0
T11	205455	395929	0	0
T13	181152	181152	0	0
T14	0	288	0	0
T23	0	424	0	0
T24	0	380088	0	0
T25	0	360	0	0
T26	0	87040	0	0
T27	0	248	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802005537	3853436	0	0
T1	14199	832	0	0
T2	1015653	10318	0	0
T3	866221	30369	0	0
T4	191735	832	0	0
T5	188087	2320	0	0
T6	2810295	13836	0	0
T7	609759	832	0	0
T8	1076956	4772	0	0
T9	30061	832	0	0
T10	8501	133	0	0
T11	410910	25209	0	0
T13	181152	0	0	0
T23	0	8	0	0
T24	0	10614	0	0
T26	0	2153	0	0
T27	0	5	0	0
T30	0	2410	0	0
T31	0	5546	0	0
T40	0	100	0	0
T41	0	3890	0	0
T42	0	3647	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T10
1	0	Covered	T3,T5,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T10
1	0	Unreachable
1	1	Covered	T3,T5,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T10
0	0	1	Unreachable
0	0	0	Covered	T3,T5,T10

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	151987649	28355267	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	151987649	659926	0	0
GntImpliesValid_A	151987649	659926	0	0
GrantKnown_A	151987649	28355267	0	0
IdxKnown_A	151987649	28355267	0	0
IndexIsCorrect_A	151987649	659926	0	0
LockArbDecision_A	151987649	0	0	0
NoReadyValidNoGrant_A	151987649	0	0	0
ReadyAndValidImplyGrant_A	151987649	659926	0	0
ReqAndReadyImplyGrant_A	151987649	659926	0	0
ReqImpliesValid_A	151987649	659926	0	0
ReqStaysHighUntilGranted0_M	151987649	0	0	0
RoundRobin_A	151987649	0	0	0
ValidKnown_A	151987649	28355267	0	0
gen_data_port_assertion.DataFlow_A	151987649	659926	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	28355267	0	0
T3	154563	428408	0	0
T4	20483	0	0	0
T5	60527	57984	0	0
T6	916392	0	0	0
T7	199386	0	0	0
T8	348288	0	0	0
T9	11490	0	0	0
T10	2405	2320	0	0
T11	205455	213864	0	0
T13	181152	0	0	0
T14	0	288	0	0
T23	0	424	0	0
T24	0	380088	0	0
T25	0	360	0	0
T26	0	87040	0	0
T27	0	248	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	659926	0	0
T3	154563	4875	0	0
T4	20483	0	0	0
T5	60527	1638	0	0
T6	916392	0	0	0
T7	199386	0	0	0
T8	348288	0	0	0
T9	11490	0	0	0
T10	2405	85	0	0
T11	205455	8564	0	0
T13	181152	0	0	0
T23	0	8	0	0
T24	0	4486	0	0
T26	0	859	0	0
T27	0	5	0	0
T40	0	100	0	0
T41	0	3890	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	659926	0	0
T3	154563	4875	0	0
T4	20483	0	0	0
T5	60527	1638	0	0
T6	916392	0	0	0
T7	199386	0	0	0
T8	348288	0	0	0
T9	11490	0	0	0
T10	2405	85	0	0
T11	205455	8564	0	0
T13	181152	0	0	0
T23	0	8	0	0
T24	0	4486	0	0
T26	0	859	0	0
T27	0	5	0	0
T40	0	100	0	0
T41	0	3890	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	28355267	0	0
T3	154563	428408	0	0
T4	20483	0	0	0
T5	60527	57984	0	0
T6	916392	0	0	0
T7	199386	0	0	0
T8	348288	0	0	0
T9	11490	0	0	0
T10	2405	2320	0	0
T11	205455	213864	0	0
T13	181152	0	0	0
T14	0	288	0	0
T23	0	424	0	0
T24	0	380088	0	0
T25	0	360	0	0
T26	0	87040	0	0
T27	0	248	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	28355267	0	0
T3	154563	428408	0	0
T4	20483	0	0	0
T5	60527	57984	0	0
T6	916392	0	0	0
T7	199386	0	0	0
T8	348288	0	0	0
T9	11490	0	0	0
T10	2405	2320	0	0
T11	205455	213864	0	0
T13	181152	0	0	0
T14	0	288	0	0
T23	0	424	0	0
T24	0	380088	0	0
T25	0	360	0	0
T26	0	87040	0	0
T27	0	248	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	659926	0	0
T3	154563	4875	0	0
T4	20483	0	0	0
T5	60527	1638	0	0
T6	916392	0	0	0
T7	199386	0	0	0
T8	348288	0	0	0
T9	11490	0	0	0
T10	2405	85	0	0
T11	205455	8564	0	0
T13	181152	0	0	0
T23	0	8	0	0
T24	0	4486	0	0
T26	0	859	0	0
T27	0	5	0	0
T40	0	100	0	0
T41	0	3890	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	659926	0	0
T3	154563	4875	0	0
T4	20483	0	0	0
T5	60527	1638	0	0
T6	916392	0	0	0
T7	199386	0	0	0
T8	348288	0	0	0
T9	11490	0	0	0
T10	2405	85	0	0
T11	205455	8564	0	0
T13	181152	0	0	0
T23	0	8	0	0
T24	0	4486	0	0
T26	0	859	0	0
T27	0	5	0	0
T40	0	100	0	0
T41	0	3890	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	659926	0	0
T3	154563	4875	0	0
T4	20483	0	0	0
T5	60527	1638	0	0
T6	916392	0	0	0
T7	199386	0	0	0
T8	348288	0	0	0
T9	11490	0	0	0
T10	2405	85	0	0
T11	205455	8564	0	0
T13	181152	0	0	0
T23	0	8	0	0
T24	0	4486	0	0
T26	0	859	0	0
T27	0	5	0	0
T40	0	100	0	0
T41	0	3890	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	659926	0	0
T3	154563	4875	0	0
T4	20483	0	0	0
T5	60527	1638	0	0
T6	916392	0	0	0
T7	199386	0	0	0
T8	348288	0	0	0
T9	11490	0	0	0
T10	2405	85	0	0
T11	205455	8564	0	0
T13	181152	0	0	0
T23	0	8	0	0
T24	0	4486	0	0
T26	0	859	0	0
T27	0	5	0	0
T40	0	100	0	0
T41	0	3890	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	28355267	0	0
T3	154563	428408	0	0
T4	20483	0	0	0
T5	60527	57984	0	0
T6	916392	0	0	0
T7	199386	0	0	0
T8	348288	0	0	0
T9	11490	0	0	0
T10	2405	2320	0	0
T11	205455	213864	0	0
T13	181152	0	0	0
T14	0	288	0	0
T23	0	424	0	0
T24	0	380088	0	0
T25	0	360	0	0
T26	0	87040	0	0
T27	0	248	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	659926	0	0
T3	154563	4875	0	0
T4	20483	0	0	0
T5	60527	1638	0	0
T6	916392	0	0	0
T7	199386	0	0	0
T8	348288	0	0	0
T9	11490	0	0	0
T10	2405	85	0	0
T11	205455	8564	0	0
T13	181152	0	0	0
T23	0	8	0	0
T24	0	4486	0	0
T26	0	859	0	0
T27	0	5	0	0
T40	0	100	0	0
T41	0	3890	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	151987649	122250342	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	151987649	892547	0	0
GntImpliesValid_A	151987649	892547	0	0
GrantKnown_A	151987649	122250342	0	0
IdxKnown_A	151987649	122250342	0	0
IndexIsCorrect_A	151987649	892547	0	0
LockArbDecision_A	151987649	0	0	0
NoReadyValidNoGrant_A	151987649	0	0	0
ReadyAndValidImplyGrant_A	151987649	892547	0	0
ReqAndReadyImplyGrant_A	151987649	892547	0	0
ReqImpliesValid_A	151987649	892547	0	0
ReqStaysHighUntilGranted0_M	151987649	0	0	0
RoundRobin_A	151987649	0	0	0
ValidKnown_A	151987649	122250342	0	0
gen_data_port_assertion.DataFlow_A	151987649	892547	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	122250342	0	0
T1	41408	41408	0	0
T2	459912	457736	0	0
T3	154563	110824	0	0
T4	20483	20483	0	0
T5	60527	0	0	0
T6	916392	912692	0	0
T7	199386	198512	0	0
T8	348288	347276	0	0
T9	11490	11490	0	0
T10	2405	0	0	0
T11	0	182065	0	0
T13	0	181152	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	892547	0	0
T2	459912	264	0	0
T3	154563	10993	0	0
T4	20483	0	0	0
T5	60527	0	0	0
T6	916392	3537	0	0
T7	199386	0	0	0
T8	348288	532	0	0
T9	11490	0	0	0
T10	2405	0	0	0
T11	205455	16645	0	0
T24	0	6128	0	0
T26	0	1294	0	0
T30	0	2410	0	0
T31	0	5546	0	0
T42	0	3647	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	892547	0	0
T2	459912	264	0	0
T3	154563	10993	0	0
T4	20483	0	0	0
T5	60527	0	0	0
T6	916392	3537	0	0
T7	199386	0	0	0
T8	348288	532	0	0
T9	11490	0	0	0
T10	2405	0	0	0
T11	205455	16645	0	0
T24	0	6128	0	0
T26	0	1294	0	0
T30	0	2410	0	0
T31	0	5546	0	0
T42	0	3647	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	122250342	0	0
T1	41408	41408	0	0
T2	459912	457736	0	0
T3	154563	110824	0	0
T4	20483	20483	0	0
T5	60527	0	0	0
T6	916392	912692	0	0
T7	199386	198512	0	0
T8	348288	347276	0	0
T9	11490	11490	0	0
T10	2405	0	0	0
T11	0	182065	0	0
T13	0	181152	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	122250342	0	0
T1	41408	41408	0	0
T2	459912	457736	0	0
T3	154563	110824	0	0
T4	20483	20483	0	0
T5	60527	0	0	0
T6	916392	912692	0	0
T7	199386	198512	0	0
T8	348288	347276	0	0
T9	11490	11490	0	0
T10	2405	0	0	0
T11	0	182065	0	0
T13	0	181152	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	892547	0	0
T2	459912	264	0	0
T3	154563	10993	0	0
T4	20483	0	0	0
T5	60527	0	0	0
T6	916392	3537	0	0
T7	199386	0	0	0
T8	348288	532	0	0
T9	11490	0	0	0
T10	2405	0	0	0
T11	205455	16645	0	0
T24	0	6128	0	0
T26	0	1294	0	0
T30	0	2410	0	0
T31	0	5546	0	0
T42	0	3647	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	892547	0	0
T2	459912	264	0	0
T3	154563	10993	0	0
T4	20483	0	0	0
T5	60527	0	0	0
T6	916392	3537	0	0
T7	199386	0	0	0
T8	348288	532	0	0
T9	11490	0	0	0
T10	2405	0	0	0
T11	205455	16645	0	0
T24	0	6128	0	0
T26	0	1294	0	0
T30	0	2410	0	0
T31	0	5546	0	0
T42	0	3647	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	892547	0	0
T2	459912	264	0	0
T3	154563	10993	0	0
T4	20483	0	0	0
T5	60527	0	0	0
T6	916392	3537	0	0
T7	199386	0	0	0
T8	348288	532	0	0
T9	11490	0	0	0
T10	2405	0	0	0
T11	205455	16645	0	0
T24	0	6128	0	0
T26	0	1294	0	0
T30	0	2410	0	0
T31	0	5546	0	0
T42	0	3647	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	892547	0	0
T2	459912	264	0	0
T3	154563	10993	0	0
T4	20483	0	0	0
T5	60527	0	0	0
T6	916392	3537	0	0
T7	199386	0	0	0
T8	348288	532	0	0
T9	11490	0	0	0
T10	2405	0	0	0
T11	205455	16645	0	0
T24	0	6128	0	0
T26	0	1294	0	0
T30	0	2410	0	0
T31	0	5546	0	0
T42	0	3647	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	122250342	0	0
T1	41408	41408	0	0
T2	459912	457736	0	0
T3	154563	110824	0	0
T4	20483	20483	0	0
T5	60527	0	0	0
T6	916392	912692	0	0
T7	199386	198512	0	0
T8	348288	347276	0	0
T9	11490	11490	0	0
T10	2405	0	0	0
T11	0	182065	0	0
T13	0	181152	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151987649	892547	0	0
T2	459912	264	0	0
T3	154563	10993	0	0
T4	20483	0	0	0
T5	60527	0	0	0
T6	916392	3537	0	0
T7	199386	0	0	0
T8	348288	532	0	0
T9	11490	0	0	0
T10	2405	0	0	0
T11	205455	16645	0	0
T24	0	6128	0	0
T26	0	1294	0	0
T30	0	2410	0	0
T31	0	5546	0	0
T42	0	3647	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	498030239	497944134	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	498030239	2300963	0	0
GntImpliesValid_A	498030239	2300963	0	0
GrantKnown_A	498030239	497944134	0	0
IdxKnown_A	498030239	497944134	0	0
IndexIsCorrect_A	498030239	2300963	0	0
LockArbDecision_A	498030239	0	0	0
NoReadyValidNoGrant_A	498030239	0	0	0
ReadyAndValidImplyGrant_A	498030239	2300963	0	0
ReqAndReadyImplyGrant_A	498030239	2300963	0	0
ReqImpliesValid_A	498030239	2300963	0	0
ReqStaysHighUntilGranted0_M	498030239	0	0	0
RoundRobin_A	498030239	5	0	955
ValidKnown_A	498030239	497944134	0	0
gen_data_port_assertion.DataFlow_A	498030239	2300963	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	497944134	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	2300963	0	0
T1	14199	832	0	0
T2	555741	10054	0	0
T3	557095	14501	0	0
T4	150769	832	0	0
T5	67033	682	0	0
T6	977511	10299	0	0
T7	210987	832	0	0
T8	380380	4240	0	0
T9	7081	832	0	0
T10	3691	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	2300963	0	0
T1	14199	832	0	0
T2	555741	10054	0	0
T3	557095	14501	0	0
T4	150769	832	0	0
T5	67033	682	0	0
T6	977511	10299	0	0
T7	210987	832	0	0
T8	380380	4240	0	0
T9	7081	832	0	0
T10	3691	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	497944134	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	497944134	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	2300963	0	0
T1	14199	832	0	0
T2	555741	10054	0	0
T3	557095	14501	0	0
T4	150769	832	0	0
T5	67033	682	0	0
T6	977511	10299	0	0
T7	210987	832	0	0
T8	380380	4240	0	0
T9	7081	832	0	0
T10	3691	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	2300963	0	0
T1	14199	832	0	0
T2	555741	10054	0	0
T3	557095	14501	0	0
T4	150769	832	0	0
T5	67033	682	0	0
T6	977511	10299	0	0
T7	210987	832	0	0
T8	380380	4240	0	0
T9	7081	832	0	0
T10	3691	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	2300963	0	0
T1	14199	832	0	0
T2	555741	10054	0	0
T3	557095	14501	0	0
T4	150769	832	0	0
T5	67033	682	0	0
T6	977511	10299	0	0
T7	210987	832	0	0
T8	380380	4240	0	0
T9	7081	832	0	0
T10	3691	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	2300963	0	0
T1	14199	832	0	0
T2	555741	10054	0	0
T3	557095	14501	0	0
T4	150769	832	0	0
T5	67033	682	0	0
T6	977511	10299	0	0
T7	210987	832	0	0
T8	380380	4240	0	0
T9	7081	832	0	0
T10	3691	48	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	5	0	955
T24	239141	1	0	1
T25	3342	0	0	1
T26	81095	0	0	1
T27	974	0	0	1
T28	230302	0	0	1
T30	182507	0	0	1
T32	137188	0	0	1
T42	144267	0	0	1
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	1252	0	0	1
T48	281185	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	497944134	0	0
T1	14199	14125	0	0
T2	555741	555684	0	0
T3	557095	556831	0	0
T4	150769	150714	0	0
T5	67033	66937	0	0
T6	977511	977456	0	0
T7	210987	210890	0	0
T8	380380	380308	0	0
T9	7081	6990	0	0
T10	3691	3616	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498030239	2300963	0	0
T1	14199	832	0	0
T2	555741	10054	0	0
T3	557095	14501	0	0
T4	150769	832	0	0
T5	67033	682	0	0
T6	977511	10299	0	0
T7	210987	832	0	0
T8	380380	4240	0	0
T9	7081	832	0	0
T10	3691	48	0	0