Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
3625 |
0 |
0 |
T53 |
19639 |
3 |
0 |
0 |
T54 |
9986 |
137 |
0 |
0 |
T55 |
13567 |
3 |
0 |
0 |
T83 |
2693 |
2 |
0 |
0 |
T84 |
5839 |
100 |
0 |
0 |
T85 |
10145 |
1 |
0 |
0 |
T86 |
19914 |
4 |
0 |
0 |
T87 |
7305 |
58 |
0 |
0 |
T88 |
13743 |
171 |
0 |
0 |
T96 |
2736 |
6 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1758 |
0 |
0 |
T55 |
13567 |
11 |
0 |
0 |
T98 |
5097 |
5 |
0 |
0 |
T105 |
100815 |
359 |
0 |
0 |
T108 |
180929 |
473 |
0 |
0 |
T136 |
19818 |
56 |
0 |
0 |
T137 |
98753 |
50 |
0 |
0 |
T138 |
14902 |
108 |
0 |
0 |
T139 |
7675 |
22 |
0 |
0 |
T140 |
4950 |
4 |
0 |
0 |
T141 |
64801 |
43 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1817 |
0 |
0 |
T55 |
13567 |
15 |
0 |
0 |
T98 |
5097 |
1 |
0 |
0 |
T105 |
100815 |
457 |
0 |
0 |
T108 |
180929 |
427 |
0 |
0 |
T136 |
19818 |
116 |
0 |
0 |
T137 |
98753 |
81 |
0 |
0 |
T138 |
14902 |
65 |
0 |
0 |
T139 |
7675 |
5 |
0 |
0 |
T140 |
4950 |
2 |
0 |
0 |
T141 |
64801 |
39 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
2102 |
0 |
0 |
T55 |
13567 |
14 |
0 |
0 |
T98 |
5097 |
10 |
0 |
0 |
T105 |
100815 |
370 |
0 |
0 |
T108 |
180929 |
437 |
0 |
0 |
T112 |
9781 |
25 |
0 |
0 |
T136 |
19818 |
32 |
0 |
0 |
T137 |
98753 |
122 |
0 |
0 |
T138 |
14902 |
27 |
0 |
0 |
T140 |
4950 |
3 |
0 |
0 |
T141 |
64801 |
82 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
8364 |
0 |
0 |
T55 |
13567 |
78 |
0 |
0 |
T98 |
5097 |
3 |
0 |
0 |
T105 |
100815 |
478 |
0 |
0 |
T108 |
180929 |
462 |
0 |
0 |
T136 |
19818 |
56 |
0 |
0 |
T137 |
98753 |
1135 |
0 |
0 |
T138 |
14902 |
77 |
0 |
0 |
T139 |
7675 |
1 |
0 |
0 |
T140 |
4950 |
5 |
0 |
0 |
T141 |
64801 |
879 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
8691 |
0 |
0 |
T55 |
13567 |
197 |
0 |
0 |
T105 |
100815 |
388 |
0 |
0 |
T108 |
180929 |
385 |
0 |
0 |
T112 |
9781 |
72 |
0 |
0 |
T136 |
19818 |
78 |
0 |
0 |
T137 |
98753 |
1400 |
0 |
0 |
T138 |
14902 |
38 |
0 |
0 |
T139 |
7675 |
12 |
0 |
0 |
T140 |
4950 |
3 |
0 |
0 |
T141 |
64801 |
478 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
8775 |
0 |
0 |
T55 |
13567 |
163 |
0 |
0 |
T98 |
5097 |
57 |
0 |
0 |
T105 |
100815 |
371 |
0 |
0 |
T108 |
180929 |
464 |
0 |
0 |
T136 |
19818 |
73 |
0 |
0 |
T137 |
98753 |
1160 |
0 |
0 |
T138 |
14902 |
54 |
0 |
0 |
T139 |
7675 |
40 |
0 |
0 |
T140 |
4950 |
138 |
0 |
0 |
T141 |
64801 |
865 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
10145 |
0 |
0 |
T55 |
13567 |
104 |
0 |
0 |
T98 |
5097 |
4 |
0 |
0 |
T105 |
100815 |
385 |
0 |
0 |
T108 |
180929 |
479 |
0 |
0 |
T136 |
19818 |
33 |
0 |
0 |
T137 |
98753 |
1105 |
0 |
0 |
T138 |
14902 |
51 |
0 |
0 |
T139 |
7675 |
63 |
0 |
0 |
T140 |
4950 |
99 |
0 |
0 |
T141 |
64801 |
643 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
8550 |
0 |
0 |
T55 |
13567 |
77 |
0 |
0 |
T98 |
5097 |
67 |
0 |
0 |
T105 |
100815 |
377 |
0 |
0 |
T108 |
180929 |
473 |
0 |
0 |
T136 |
19818 |
74 |
0 |
0 |
T137 |
98753 |
1113 |
0 |
0 |
T138 |
14902 |
37 |
0 |
0 |
T139 |
7675 |
38 |
0 |
0 |
T140 |
4950 |
131 |
0 |
0 |
T141 |
64801 |
619 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
8864 |
0 |
0 |
T55 |
13567 |
123 |
0 |
0 |
T105 |
100815 |
379 |
0 |
0 |
T108 |
180929 |
430 |
0 |
0 |
T112 |
9781 |
4 |
0 |
0 |
T136 |
19818 |
71 |
0 |
0 |
T137 |
98753 |
1122 |
0 |
0 |
T138 |
14902 |
61 |
0 |
0 |
T139 |
7675 |
24 |
0 |
0 |
T140 |
4950 |
132 |
0 |
0 |
T141 |
64801 |
813 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
8296 |
0 |
0 |
T55 |
13567 |
119 |
0 |
0 |
T98 |
5097 |
1 |
0 |
0 |
T105 |
100815 |
428 |
0 |
0 |
T108 |
180929 |
471 |
0 |
0 |
T136 |
19818 |
35 |
0 |
0 |
T137 |
98753 |
829 |
0 |
0 |
T138 |
14902 |
11 |
0 |
0 |
T139 |
7675 |
14 |
0 |
0 |
T140 |
4950 |
7 |
0 |
0 |
T141 |
64801 |
765 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
8162 |
0 |
0 |
T55 |
13567 |
96 |
0 |
0 |
T98 |
5097 |
88 |
0 |
0 |
T105 |
100815 |
373 |
0 |
0 |
T108 |
180929 |
523 |
0 |
0 |
T136 |
19818 |
73 |
0 |
0 |
T137 |
98753 |
867 |
0 |
0 |
T138 |
14902 |
31 |
0 |
0 |
T139 |
7675 |
4 |
0 |
0 |
T140 |
4950 |
6 |
0 |
0 |
T141 |
64801 |
671 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4428 |
0 |
0 |
T55 |
13567 |
59 |
0 |
0 |
T98 |
5097 |
44 |
0 |
0 |
T105 |
100815 |
359 |
0 |
0 |
T108 |
180929 |
466 |
0 |
0 |
T136 |
19818 |
71 |
0 |
0 |
T137 |
98753 |
469 |
0 |
0 |
T138 |
14902 |
52 |
0 |
0 |
T139 |
7675 |
24 |
0 |
0 |
T140 |
4950 |
56 |
0 |
0 |
T141 |
64801 |
263 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4233 |
0 |
0 |
T55 |
13567 |
45 |
0 |
0 |
T98 |
5097 |
30 |
0 |
0 |
T105 |
100815 |
440 |
0 |
0 |
T108 |
180929 |
432 |
0 |
0 |
T112 |
9781 |
113 |
0 |
0 |
T136 |
19818 |
63 |
0 |
0 |
T137 |
98753 |
433 |
0 |
0 |
T138 |
14902 |
26 |
0 |
0 |
T139 |
7675 |
16 |
0 |
0 |
T141 |
64801 |
350 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4493 |
0 |
0 |
T55 |
13567 |
87 |
0 |
0 |
T98 |
5097 |
23 |
0 |
0 |
T105 |
100815 |
374 |
0 |
0 |
T108 |
180929 |
473 |
0 |
0 |
T136 |
19818 |
57 |
0 |
0 |
T137 |
98753 |
602 |
0 |
0 |
T138 |
14902 |
63 |
0 |
0 |
T139 |
7675 |
36 |
0 |
0 |
T140 |
4950 |
59 |
0 |
0 |
T141 |
64801 |
259 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
3986 |
0 |
0 |
T55 |
13567 |
44 |
0 |
0 |
T98 |
5097 |
30 |
0 |
0 |
T105 |
100815 |
380 |
0 |
0 |
T108 |
180929 |
421 |
0 |
0 |
T136 |
19818 |
27 |
0 |
0 |
T137 |
98753 |
418 |
0 |
0 |
T138 |
14902 |
13 |
0 |
0 |
T139 |
7675 |
37 |
0 |
0 |
T140 |
4950 |
3 |
0 |
0 |
T141 |
64801 |
330 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4301 |
0 |
0 |
T55 |
13567 |
126 |
0 |
0 |
T98 |
5097 |
3 |
0 |
0 |
T105 |
100815 |
408 |
0 |
0 |
T108 |
180929 |
412 |
0 |
0 |
T112 |
9781 |
16 |
0 |
0 |
T136 |
19818 |
81 |
0 |
0 |
T137 |
98753 |
440 |
0 |
0 |
T138 |
14902 |
40 |
0 |
0 |
T139 |
7675 |
22 |
0 |
0 |
T141 |
64801 |
226 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
3946 |
0 |
0 |
T55 |
13567 |
65 |
0 |
0 |
T98 |
5097 |
29 |
0 |
0 |
T105 |
100815 |
447 |
0 |
0 |
T108 |
180929 |
425 |
0 |
0 |
T136 |
19818 |
119 |
0 |
0 |
T137 |
98753 |
322 |
0 |
0 |
T138 |
14902 |
103 |
0 |
0 |
T139 |
7675 |
7 |
0 |
0 |
T140 |
4950 |
44 |
0 |
0 |
T141 |
64801 |
211 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4213 |
0 |
0 |
T55 |
13567 |
43 |
0 |
0 |
T98 |
5097 |
40 |
0 |
0 |
T105 |
100815 |
391 |
0 |
0 |
T108 |
180929 |
451 |
0 |
0 |
T136 |
19818 |
89 |
0 |
0 |
T137 |
98753 |
395 |
0 |
0 |
T138 |
14902 |
25 |
0 |
0 |
T139 |
7675 |
2 |
0 |
0 |
T140 |
4950 |
39 |
0 |
0 |
T141 |
64801 |
240 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4401 |
0 |
0 |
T55 |
13567 |
90 |
0 |
0 |
T105 |
100815 |
421 |
0 |
0 |
T108 |
180929 |
434 |
0 |
0 |
T112 |
9781 |
50 |
0 |
0 |
T136 |
19818 |
91 |
0 |
0 |
T137 |
98753 |
381 |
0 |
0 |
T138 |
14902 |
41 |
0 |
0 |
T139 |
7675 |
19 |
0 |
0 |
T140 |
4950 |
45 |
0 |
0 |
T141 |
64801 |
292 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4357 |
0 |
0 |
T55 |
13567 |
55 |
0 |
0 |
T98 |
5097 |
2 |
0 |
0 |
T105 |
100815 |
397 |
0 |
0 |
T108 |
180929 |
460 |
0 |
0 |
T136 |
19818 |
56 |
0 |
0 |
T137 |
98753 |
405 |
0 |
0 |
T138 |
14902 |
80 |
0 |
0 |
T139 |
7675 |
3 |
0 |
0 |
T140 |
4950 |
42 |
0 |
0 |
T141 |
64801 |
319 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4192 |
0 |
0 |
T55 |
13567 |
31 |
0 |
0 |
T98 |
5097 |
3 |
0 |
0 |
T105 |
100815 |
419 |
0 |
0 |
T108 |
180929 |
502 |
0 |
0 |
T136 |
19818 |
90 |
0 |
0 |
T137 |
98753 |
394 |
0 |
0 |
T138 |
14902 |
8 |
0 |
0 |
T139 |
7675 |
12 |
0 |
0 |
T140 |
4950 |
55 |
0 |
0 |
T141 |
64801 |
325 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4284 |
0 |
0 |
T55 |
13567 |
24 |
0 |
0 |
T98 |
5097 |
22 |
0 |
0 |
T105 |
100815 |
380 |
0 |
0 |
T108 |
180929 |
452 |
0 |
0 |
T136 |
19818 |
101 |
0 |
0 |
T137 |
98753 |
364 |
0 |
0 |
T138 |
14902 |
42 |
0 |
0 |
T139 |
7675 |
16 |
0 |
0 |
T140 |
4950 |
5 |
0 |
0 |
T141 |
64801 |
387 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4403 |
0 |
0 |
T55 |
13567 |
107 |
0 |
0 |
T98 |
5097 |
40 |
0 |
0 |
T105 |
100815 |
395 |
0 |
0 |
T108 |
180929 |
459 |
0 |
0 |
T136 |
19818 |
61 |
0 |
0 |
T137 |
98753 |
465 |
0 |
0 |
T138 |
14902 |
46 |
0 |
0 |
T139 |
7675 |
17 |
0 |
0 |
T140 |
4950 |
44 |
0 |
0 |
T141 |
64801 |
276 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4420 |
0 |
0 |
T55 |
13567 |
87 |
0 |
0 |
T105 |
100815 |
402 |
0 |
0 |
T108 |
180929 |
504 |
0 |
0 |
T112 |
9781 |
40 |
0 |
0 |
T136 |
19818 |
74 |
0 |
0 |
T137 |
98753 |
516 |
0 |
0 |
T138 |
14902 |
13 |
0 |
0 |
T139 |
7675 |
24 |
0 |
0 |
T140 |
4950 |
49 |
0 |
0 |
T141 |
64801 |
332 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4257 |
0 |
0 |
T55 |
13567 |
45 |
0 |
0 |
T105 |
100815 |
412 |
0 |
0 |
T108 |
180929 |
437 |
0 |
0 |
T112 |
9781 |
26 |
0 |
0 |
T136 |
19818 |
87 |
0 |
0 |
T137 |
98753 |
451 |
0 |
0 |
T138 |
14902 |
75 |
0 |
0 |
T139 |
7675 |
21 |
0 |
0 |
T140 |
4950 |
4 |
0 |
0 |
T141 |
64801 |
297 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4338 |
0 |
0 |
T55 |
13567 |
6 |
0 |
0 |
T98 |
5097 |
6 |
0 |
0 |
T105 |
100815 |
401 |
0 |
0 |
T108 |
180929 |
444 |
0 |
0 |
T136 |
19818 |
71 |
0 |
0 |
T137 |
98753 |
475 |
0 |
0 |
T138 |
14902 |
60 |
0 |
0 |
T139 |
7675 |
27 |
0 |
0 |
T140 |
4950 |
2 |
0 |
0 |
T141 |
64801 |
234 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4369 |
0 |
0 |
T55 |
13567 |
32 |
0 |
0 |
T98 |
5097 |
4 |
0 |
0 |
T105 |
100815 |
404 |
0 |
0 |
T108 |
180929 |
447 |
0 |
0 |
T136 |
19818 |
64 |
0 |
0 |
T137 |
98753 |
459 |
0 |
0 |
T138 |
14902 |
19 |
0 |
0 |
T139 |
7675 |
48 |
0 |
0 |
T140 |
4950 |
3 |
0 |
0 |
T141 |
64801 |
261 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
5147 |
0 |
0 |
T55 |
13567 |
53 |
0 |
0 |
T98 |
5097 |
10 |
0 |
0 |
T105 |
100815 |
414 |
0 |
0 |
T108 |
180929 |
545 |
0 |
0 |
T136 |
19818 |
71 |
0 |
0 |
T137 |
98753 |
475 |
0 |
0 |
T138 |
14902 |
50 |
0 |
0 |
T139 |
7675 |
10 |
0 |
0 |
T140 |
4950 |
62 |
0 |
0 |
T141 |
64801 |
374 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4524 |
0 |
0 |
T55 |
13567 |
37 |
0 |
0 |
T98 |
5097 |
1 |
0 |
0 |
T105 |
100815 |
390 |
0 |
0 |
T108 |
180929 |
465 |
0 |
0 |
T136 |
19818 |
28 |
0 |
0 |
T137 |
98753 |
568 |
0 |
0 |
T138 |
14902 |
25 |
0 |
0 |
T139 |
7675 |
38 |
0 |
0 |
T140 |
4950 |
72 |
0 |
0 |
T141 |
64801 |
278 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4454 |
0 |
0 |
T55 |
13567 |
18 |
0 |
0 |
T105 |
100815 |
472 |
0 |
0 |
T108 |
180929 |
472 |
0 |
0 |
T112 |
9781 |
44 |
0 |
0 |
T136 |
19818 |
76 |
0 |
0 |
T137 |
98753 |
385 |
0 |
0 |
T138 |
14902 |
44 |
0 |
0 |
T139 |
7675 |
9 |
0 |
0 |
T140 |
4950 |
44 |
0 |
0 |
T141 |
64801 |
360 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4038 |
0 |
0 |
T55 |
13567 |
58 |
0 |
0 |
T98 |
5097 |
2 |
0 |
0 |
T105 |
100815 |
417 |
0 |
0 |
T108 |
180929 |
419 |
0 |
0 |
T136 |
19818 |
23 |
0 |
0 |
T137 |
98753 |
475 |
0 |
0 |
T138 |
14902 |
68 |
0 |
0 |
T139 |
7675 |
7 |
0 |
0 |
T140 |
4950 |
58 |
0 |
0 |
T141 |
64801 |
295 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4186 |
0 |
0 |
T55 |
13567 |
55 |
0 |
0 |
T98 |
5097 |
8 |
0 |
0 |
T105 |
100815 |
333 |
0 |
0 |
T108 |
180929 |
438 |
0 |
0 |
T136 |
19818 |
71 |
0 |
0 |
T137 |
98753 |
402 |
0 |
0 |
T138 |
14902 |
45 |
0 |
0 |
T139 |
7675 |
40 |
0 |
0 |
T140 |
4950 |
35 |
0 |
0 |
T141 |
64801 |
355 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4578 |
0 |
0 |
T55 |
13567 |
6 |
0 |
0 |
T98 |
5097 |
39 |
0 |
0 |
T105 |
100815 |
420 |
0 |
0 |
T108 |
180929 |
496 |
0 |
0 |
T136 |
19818 |
36 |
0 |
0 |
T137 |
98753 |
377 |
0 |
0 |
T138 |
14902 |
41 |
0 |
0 |
T139 |
7675 |
21 |
0 |
0 |
T140 |
4950 |
2 |
0 |
0 |
T141 |
64801 |
285 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4463 |
0 |
0 |
T55 |
13567 |
60 |
0 |
0 |
T98 |
5097 |
29 |
0 |
0 |
T105 |
100815 |
382 |
0 |
0 |
T108 |
180929 |
398 |
0 |
0 |
T136 |
19818 |
55 |
0 |
0 |
T137 |
98753 |
498 |
0 |
0 |
T138 |
14902 |
57 |
0 |
0 |
T139 |
7675 |
8 |
0 |
0 |
T140 |
4950 |
4 |
0 |
0 |
T141 |
64801 |
186 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
4356 |
0 |
0 |
T55 |
13567 |
37 |
0 |
0 |
T98 |
5097 |
2 |
0 |
0 |
T105 |
100815 |
406 |
0 |
0 |
T108 |
180929 |
459 |
0 |
0 |
T136 |
19818 |
60 |
0 |
0 |
T137 |
98753 |
254 |
0 |
0 |
T138 |
14902 |
42 |
0 |
0 |
T139 |
7675 |
31 |
0 |
0 |
T140 |
4950 |
57 |
0 |
0 |
T141 |
64801 |
251 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
2021 |
0 |
0 |
T55 |
13567 |
16 |
0 |
0 |
T98 |
5097 |
10 |
0 |
0 |
T105 |
100815 |
438 |
0 |
0 |
T108 |
180929 |
400 |
0 |
0 |
T136 |
19818 |
125 |
0 |
0 |
T137 |
98753 |
114 |
0 |
0 |
T138 |
14902 |
35 |
0 |
0 |
T139 |
7675 |
48 |
0 |
0 |
T140 |
4950 |
4 |
0 |
0 |
T141 |
64801 |
59 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1823 |
0 |
0 |
T55 |
13567 |
22 |
0 |
0 |
T98 |
5097 |
1 |
0 |
0 |
T105 |
100815 |
406 |
0 |
0 |
T108 |
180929 |
458 |
0 |
0 |
T136 |
19818 |
46 |
0 |
0 |
T137 |
98753 |
84 |
0 |
0 |
T138 |
14902 |
21 |
0 |
0 |
T139 |
7675 |
14 |
0 |
0 |
T140 |
4950 |
8 |
0 |
0 |
T141 |
64801 |
44 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1856 |
0 |
0 |
T55 |
13567 |
20 |
0 |
0 |
T98 |
5097 |
1 |
0 |
0 |
T105 |
100815 |
422 |
0 |
0 |
T108 |
180929 |
432 |
0 |
0 |
T112 |
9781 |
12 |
0 |
0 |
T136 |
19818 |
47 |
0 |
0 |
T137 |
98753 |
130 |
0 |
0 |
T138 |
14902 |
28 |
0 |
0 |
T140 |
4950 |
7 |
0 |
0 |
T141 |
64801 |
70 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
2070 |
0 |
0 |
T55 |
13567 |
20 |
0 |
0 |
T98 |
5097 |
15 |
0 |
0 |
T105 |
100815 |
456 |
0 |
0 |
T108 |
180929 |
497 |
0 |
0 |
T136 |
19818 |
84 |
0 |
0 |
T137 |
98753 |
87 |
0 |
0 |
T138 |
14902 |
46 |
0 |
0 |
T139 |
7675 |
28 |
0 |
0 |
T140 |
4950 |
1 |
0 |
0 |
T141 |
64801 |
66 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
2219 |
0 |
0 |
T55 |
13567 |
18 |
0 |
0 |
T98 |
5097 |
7 |
0 |
0 |
T105 |
100815 |
320 |
0 |
0 |
T108 |
180929 |
476 |
0 |
0 |
T136 |
19818 |
86 |
0 |
0 |
T137 |
98753 |
134 |
0 |
0 |
T138 |
14902 |
56 |
0 |
0 |
T139 |
7675 |
32 |
0 |
0 |
T140 |
4950 |
26 |
0 |
0 |
T141 |
64801 |
116 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
3548 |
0 |
0 |
T15 |
5488 |
35 |
0 |
0 |
T20 |
0 |
50 |
0 |
0 |
T34 |
8868 |
0 |
0 |
0 |
T52 |
1368 |
0 |
0 |
0 |
T71 |
459436 |
0 |
0 |
0 |
T80 |
2073 |
0 |
0 |
0 |
T116 |
2065 |
0 |
0 |
0 |
T117 |
10291 |
0 |
0 |
0 |
T118 |
453748 |
0 |
0 |
0 |
T142 |
0 |
55 |
0 |
0 |
T143 |
0 |
39 |
0 |
0 |
T144 |
0 |
14 |
0 |
0 |
T145 |
0 |
20 |
0 |
0 |
T146 |
0 |
29 |
0 |
0 |
T147 |
0 |
4 |
0 |
0 |
T148 |
0 |
34 |
0 |
0 |
T149 |
0 |
39 |
0 |
0 |
T150 |
80378 |
0 |
0 |
0 |
T151 |
200914 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1861 |
0 |
0 |
T55 |
13567 |
12 |
0 |
0 |
T98 |
5097 |
7 |
0 |
0 |
T105 |
100815 |
368 |
0 |
0 |
T108 |
180929 |
484 |
0 |
0 |
T112 |
9781 |
1 |
0 |
0 |
T136 |
19818 |
92 |
0 |
0 |
T137 |
98753 |
99 |
0 |
0 |
T138 |
14902 |
64 |
0 |
0 |
T140 |
4950 |
1 |
0 |
0 |
T141 |
64801 |
59 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1909 |
0 |
0 |
T55 |
13567 |
17 |
0 |
0 |
T98 |
5097 |
1 |
0 |
0 |
T105 |
100815 |
336 |
0 |
0 |
T108 |
180929 |
509 |
0 |
0 |
T136 |
19818 |
64 |
0 |
0 |
T137 |
98753 |
92 |
0 |
0 |
T138 |
14902 |
31 |
0 |
0 |
T139 |
7675 |
16 |
0 |
0 |
T140 |
4950 |
6 |
0 |
0 |
T141 |
64801 |
80 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1686 |
0 |
0 |
T55 |
13567 |
16 |
0 |
0 |
T98 |
5097 |
18 |
0 |
0 |
T105 |
100815 |
414 |
0 |
0 |
T108 |
180929 |
476 |
0 |
0 |
T136 |
19818 |
56 |
0 |
0 |
T137 |
98753 |
50 |
0 |
0 |
T138 |
14902 |
39 |
0 |
0 |
T139 |
7675 |
35 |
0 |
0 |
T140 |
4950 |
4 |
0 |
0 |
T141 |
64801 |
29 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1714 |
0 |
0 |
T55 |
13567 |
15 |
0 |
0 |
T98 |
5097 |
10 |
0 |
0 |
T105 |
100815 |
398 |
0 |
0 |
T108 |
180929 |
463 |
0 |
0 |
T136 |
19818 |
48 |
0 |
0 |
T137 |
98753 |
60 |
0 |
0 |
T138 |
14902 |
56 |
0 |
0 |
T139 |
7675 |
19 |
0 |
0 |
T140 |
4950 |
2 |
0 |
0 |
T141 |
64801 |
25 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1658 |
0 |
0 |
T55 |
13567 |
7 |
0 |
0 |
T98 |
5097 |
2 |
0 |
0 |
T105 |
100815 |
438 |
0 |
0 |
T108 |
180929 |
413 |
0 |
0 |
T136 |
19818 |
22 |
0 |
0 |
T137 |
98753 |
59 |
0 |
0 |
T138 |
14902 |
43 |
0 |
0 |
T139 |
7675 |
8 |
0 |
0 |
T140 |
4950 |
4 |
0 |
0 |
T141 |
64801 |
42 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1636 |
0 |
0 |
T55 |
13567 |
12 |
0 |
0 |
T98 |
5097 |
7 |
0 |
0 |
T105 |
100815 |
381 |
0 |
0 |
T108 |
180929 |
471 |
0 |
0 |
T136 |
19818 |
36 |
0 |
0 |
T137 |
98753 |
71 |
0 |
0 |
T138 |
14902 |
50 |
0 |
0 |
T139 |
7675 |
13 |
0 |
0 |
T140 |
4950 |
3 |
0 |
0 |
T141 |
64801 |
64 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
2320 |
0 |
0 |
T55 |
13567 |
24 |
0 |
0 |
T98 |
5097 |
10 |
0 |
0 |
T105 |
100815 |
422 |
0 |
0 |
T108 |
180929 |
427 |
0 |
0 |
T136 |
19818 |
98 |
0 |
0 |
T137 |
98753 |
163 |
0 |
0 |
T138 |
14902 |
51 |
0 |
0 |
T139 |
7675 |
41 |
0 |
0 |
T140 |
4950 |
14 |
0 |
0 |
T141 |
64801 |
122 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1608 |
0 |
0 |
T55 |
13567 |
14 |
0 |
0 |
T105 |
100815 |
391 |
0 |
0 |
T108 |
180929 |
451 |
0 |
0 |
T136 |
19818 |
35 |
0 |
0 |
T137 |
98753 |
79 |
0 |
0 |
T138 |
14902 |
27 |
0 |
0 |
T139 |
7675 |
9 |
0 |
0 |
T140 |
4950 |
3 |
0 |
0 |
T141 |
64801 |
29 |
0 |
0 |
T152 |
93591 |
56 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
2575 |
0 |
0 |
T55 |
13567 |
4 |
0 |
0 |
T98 |
5097 |
22 |
0 |
0 |
T105 |
100815 |
386 |
0 |
0 |
T108 |
180929 |
462 |
0 |
0 |
T136 |
19818 |
77 |
0 |
0 |
T137 |
98753 |
215 |
0 |
0 |
T138 |
14902 |
82 |
0 |
0 |
T139 |
7675 |
5 |
0 |
0 |
T140 |
4950 |
9 |
0 |
0 |
T141 |
64801 |
121 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1885 |
0 |
0 |
T55 |
13567 |
12 |
0 |
0 |
T98 |
5097 |
7 |
0 |
0 |
T105 |
100815 |
386 |
0 |
0 |
T108 |
180929 |
485 |
0 |
0 |
T112 |
9781 |
16 |
0 |
0 |
T136 |
19818 |
42 |
0 |
0 |
T137 |
98753 |
83 |
0 |
0 |
T138 |
14902 |
78 |
0 |
0 |
T139 |
7675 |
29 |
0 |
0 |
T141 |
64801 |
59 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1666 |
0 |
0 |
T55 |
13567 |
5 |
0 |
0 |
T105 |
100815 |
421 |
0 |
0 |
T108 |
180929 |
422 |
0 |
0 |
T136 |
19818 |
58 |
0 |
0 |
T137 |
98753 |
19 |
0 |
0 |
T138 |
14902 |
61 |
0 |
0 |
T139 |
7675 |
55 |
0 |
0 |
T140 |
4950 |
1 |
0 |
0 |
T141 |
64801 |
27 |
0 |
0 |
T152 |
93591 |
76 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1659 |
0 |
0 |
T55 |
13567 |
14 |
0 |
0 |
T98 |
5097 |
3 |
0 |
0 |
T105 |
100815 |
443 |
0 |
0 |
T108 |
180929 |
447 |
0 |
0 |
T112 |
9781 |
1 |
0 |
0 |
T136 |
19818 |
52 |
0 |
0 |
T137 |
98753 |
65 |
0 |
0 |
T138 |
14902 |
54 |
0 |
0 |
T140 |
4950 |
7 |
0 |
0 |
T141 |
64801 |
31 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1730 |
0 |
0 |
T55 |
13567 |
10 |
0 |
0 |
T105 |
100815 |
510 |
0 |
0 |
T108 |
180929 |
474 |
0 |
0 |
T136 |
19818 |
74 |
0 |
0 |
T137 |
98753 |
68 |
0 |
0 |
T138 |
14902 |
23 |
0 |
0 |
T139 |
7675 |
9 |
0 |
0 |
T140 |
4950 |
8 |
0 |
0 |
T141 |
64801 |
37 |
0 |
0 |
T152 |
93591 |
36 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1537 |
0 |
0 |
T55 |
13567 |
9 |
0 |
0 |
T105 |
100815 |
375 |
0 |
0 |
T108 |
180929 |
445 |
0 |
0 |
T112 |
9781 |
7 |
0 |
0 |
T136 |
19818 |
78 |
0 |
0 |
T137 |
98753 |
40 |
0 |
0 |
T138 |
14902 |
42 |
0 |
0 |
T139 |
7675 |
22 |
0 |
0 |
T140 |
4950 |
6 |
0 |
0 |
T141 |
64801 |
23 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1829 |
0 |
0 |
T55 |
13567 |
2 |
0 |
0 |
T98 |
5097 |
12 |
0 |
0 |
T105 |
100815 |
413 |
0 |
0 |
T108 |
180929 |
429 |
0 |
0 |
T136 |
19818 |
81 |
0 |
0 |
T137 |
98753 |
78 |
0 |
0 |
T138 |
14902 |
71 |
0 |
0 |
T139 |
7675 |
25 |
0 |
0 |
T140 |
4950 |
5 |
0 |
0 |
T141 |
64801 |
36 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
500315288 |
1805 |
0 |
0 |
T55 |
13567 |
6 |
0 |
0 |
T98 |
5097 |
2 |
0 |
0 |
T105 |
100815 |
402 |
0 |
0 |
T108 |
180929 |
515 |
0 |
0 |
T136 |
19818 |
76 |
0 |
0 |
T137 |
98753 |
80 |
0 |
0 |
T138 |
14902 |
22 |
0 |
0 |
T139 |
7675 |
26 |
0 |
0 |
T140 |
4950 |
4 |
0 |
0 |
T141 |
64801 |
40 |
0 |
0 |