Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3768218	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4437059

1

T1

62755

T2

35349

T3

888

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4509086	1			T1	104387		T2	58298		T3	5
values[0x0]	1847640	1			T1	32174		T2	18238		T3	433
values[0x1]	1848551	1			T1	32104		T2	18118		T3	454

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2671461	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5533816

1

T1

96237

T2

54320

T3

889

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32205	1			T1	528		T2	398		T3	1
valid_sources[0x01]	29530	1			T1	593		T2	364		T3	1
valid_sources[0x02]	32319	1			T1	545		T2	357		T3	5
valid_sources[0x03]	32538	1			T1	786		T2	441		T3	3
valid_sources[0x04]	29182	1			T1	617		T2	413		T3	7
valid_sources[0x05]	27405	1			T1	528		T2	399		T3	3
valid_sources[0x06]	31828	1			T1	721		T2	318		T3	4
valid_sources[0x07]	29493	1			T1	529		T2	413		T3	1
valid_sources[0x08]	31392	1			T1	600		T2	372		T3	5
valid_sources[0x09]	33093	1			T1	871		T2	389		T3	4
valid_sources[0x0a]	37086	1			T1	637		T2	402		T3	3
valid_sources[0x0b]	30671	1			T1	571		T2	393		T3	1
valid_sources[0x0c]	34321	1			T1	733		T2	315		T3	2
valid_sources[0x0d]	29000	1			T1	778		T2	348		T3	4
valid_sources[0x0e]	33261	1			T1	679		T2	421		T3	4
valid_sources[0x0f]	29895	1			T1	678		T2	365		T3	4
valid_sources[0x10]	29426	1			T1	742		T2	384		T3	6
valid_sources[0x11]	29582	1			T1	625		T2	303		T3	6
valid_sources[0x12]	33310	1			T1	619		T2	355		T3	3
valid_sources[0x13]	30296	1			T1	746		T2	319		T3	3
valid_sources[0x14]	43439	1			T1	623		T2	271		T3	1
valid_sources[0x15]	30818	1			T1	684		T2	347		T3	6
valid_sources[0x16]	33910	1			T1	673		T2	414		T3	3
valid_sources[0x17]	31467	1			T1	724		T2	351		T3	3
valid_sources[0x18]	35715	1			T1	781		T2	383		T3	2
valid_sources[0x19]	29323	1			T1	645		T2	308		T3	2
valid_sources[0x1a]	29265	1			T1	683		T2	459		T3	5
valid_sources[0x1b]	28659	1			T1	730		T2	380		T3	3
valid_sources[0x1c]	31282	1			T1	718		T2	322		T3	3
valid_sources[0x1d]	30533	1			T1	756		T2	352		T3	3
valid_sources[0x1e]	33412	1			T1	562		T2	307		T3	1
valid_sources[0x1f]	34574	1			T1	656		T2	452		T3	4
valid_sources[0x20]	32935	1			T1	677		T2	352		T3	5
valid_sources[0x21]	28954	1			T1	811		T2	382		T3	2
valid_sources[0x22]	29649	1			T1	697		T2	469		T3	6
valid_sources[0x23]	30332	1			T1	660		T2	330		T3	4
valid_sources[0x24]	29251	1			T1	561		T2	359		T3	2
valid_sources[0x25]	32176	1			T1	587		T2	336		T3	1
valid_sources[0x26]	30930	1			T1	721		T2	461		T3	1
valid_sources[0x27]	31879	1			T1	423		T2	295		T3	3
valid_sources[0x28]	33115	1			T1	773		T2	418		T3	2
valid_sources[0x29]	33103	1			T1	644		T2	282		T3	7
valid_sources[0x2a]	27983	1			T1	717		T2	273		T3	1
valid_sources[0x2b]	32407	1			T1	603		T2	416		T3	4
valid_sources[0x2c]	41474	1			T1	719		T2	470		T3	3
valid_sources[0x2d]	34432	1			T1	635		T2	274		T3	2
valid_sources[0x2e]	32044	1			T1	585		T2	304		T3	3
valid_sources[0x2f]	32849	1			T1	609		T2	394		T3	6
valid_sources[0x30]	32084	1			T1	626		T2	286		T3	4
valid_sources[0x31]	28503	1			T1	611		T2	446		T3	3
valid_sources[0x32]	30900	1			T1	767		T2	357		T3	2
valid_sources[0x33]	38521	1			T1	717		T2	381		T3	3
valid_sources[0x34]	32548	1			T1	606		T2	332		T3	5
valid_sources[0x35]	30180	1			T1	911		T2	249		T3	2
valid_sources[0x36]	31581	1			T1	637		T2	300		T3	2
valid_sources[0x37]	31258	1			T1	636		T2	297		T3	2
valid_sources[0x38]	34817	1			T1	695		T2	385		T3	1
valid_sources[0x39]	32022	1			T1	580		T2	269		T3	4
valid_sources[0x3a]	28965	1			T1	686		T2	373		T3	8
valid_sources[0x3b]	32012	1			T1	652		T2	344		T3	3
valid_sources[0x3c]	39517	1			T1	646		T2	374		T3	2
valid_sources[0x3d]	29275	1			T1	634		T2	396		T3	5
valid_sources[0x3e]	35229	1			T1	735		T2	444		T3	3
valid_sources[0x3f]	30262	1			T1	588		T2	474		T3	4
valid_sources[0x40]	32565	1			T1	641		T2	291		T3	6
valid_sources[0x41]	30914	1			T1	460		T2	397		T3	4
valid_sources[0x42]	31192	1			T1	746		T2	371		T3	1
valid_sources[0x43]	30670	1			T1	674		T2	276		T3	3
valid_sources[0x44]	30214	1			T1	723		T2	395		T3	1
valid_sources[0x45]	32507	1			T1	633		T2	389		T3	4
valid_sources[0x46]	30333	1			T1	594		T2	428		T3	3
valid_sources[0x47]	32424	1			T1	677		T2	443		T3	5
valid_sources[0x48]	31996	1			T1	631		T2	308		T3	2
valid_sources[0x49]	30965	1			T1	584		T2	246		T3	3
valid_sources[0x4a]	32310	1			T1	541		T2	370		T3	3
valid_sources[0x4b]	32334	1			T1	584		T2	328		T3	3
valid_sources[0x4c]	30837	1			T1	556		T2	354		T3	3
valid_sources[0x4d]	30090	1			T1	848		T2	303		T3	4
valid_sources[0x4e]	29535	1			T1	608		T2	415		T3	4
valid_sources[0x4f]	29982	1			T1	790		T2	263		T3	3
valid_sources[0x50]	30440	1			T1	625		T2	403		T3	2
valid_sources[0x51]	30344	1			T1	675		T2	486		T3	4
valid_sources[0x52]	30987	1			T1	592		T2	324		T3	2
valid_sources[0x53]	32677	1			T1	702		T2	253		T3	7
valid_sources[0x54]	30288	1			T1	546		T2	424		T4	34
valid_sources[0x55]	42861	1			T1	670		T2	347		T3	6
valid_sources[0x56]	33784	1			T1	639		T2	346		T3	6
valid_sources[0x57]	30591	1			T1	695		T2	316		T3	2
valid_sources[0x58]	34244	1			T1	790		T2	309		T3	5
valid_sources[0x59]	33033	1			T1	837		T2	508		T3	2
valid_sources[0x5a]	30423	1			T1	542		T2	360		T3	3
valid_sources[0x5b]	31085	1			T1	654		T2	423		T3	5
valid_sources[0x5c]	32337	1			T1	566		T2	456		T3	4
valid_sources[0x5d]	37265	1			T1	715		T2	399		T3	3
valid_sources[0x5e]	35696	1			T1	678		T2	409		T3	3
valid_sources[0x5f]	31870	1			T1	741		T2	480		T3	3
valid_sources[0x60]	31838	1			T1	623		T2	481		T3	3
valid_sources[0x61]	30766	1			T1	651		T2	375		T3	5
valid_sources[0x62]	32362	1			T1	562		T2	406		T3	2
valid_sources[0x63]	30577	1			T1	695		T2	431		T3	2
valid_sources[0x64]	27753	1			T1	590		T2	382		T3	6
valid_sources[0x65]	32325	1			T1	694		T2	218		T3	4
valid_sources[0x66]	30385	1			T1	856		T2	447		T3	3
valid_sources[0x67]	37340	1			T1	572		T2	497		T3	5
valid_sources[0x68]	29328	1			T1	544		T2	357		T3	5
valid_sources[0x69]	29992	1			T1	658		T2	333		T3	2
valid_sources[0x6a]	32965	1			T1	785		T2	339		T3	3
valid_sources[0x6b]	30379	1			T1	607		T2	387		T3	5
valid_sources[0x6c]	29134	1			T1	733		T2	326		T3	3
valid_sources[0x6d]	29973	1			T1	510		T2	535		T3	3
valid_sources[0x6e]	31145	1			T1	771		T2	328		T3	7
valid_sources[0x6f]	30710	1			T1	567		T2	327		T3	4
valid_sources[0x70]	35853	1			T1	707		T2	382		T3	6
valid_sources[0x71]	31944	1			T1	683		T2	403		T3	2
valid_sources[0x72]	29929	1			T1	654		T2	394		T3	3
valid_sources[0x73]	32003	1			T1	695		T2	491		T3	4
valid_sources[0x74]	31214	1			T1	656		T2	396		T3	6
valid_sources[0x75]	31355	1			T1	662		T2	288		T3	2
valid_sources[0x76]	33097	1			T1	710		T2	441		T3	2
valid_sources[0x77]	31897	1			T1	597		T2	467		T3	4
valid_sources[0x78]	31869	1			T1	667		T2	410		T3	1
valid_sources[0x79]	31928	1			T1	624		T2	429		T3	4
valid_sources[0x7a]	27485	1			T1	588		T2	351		T3	7
valid_sources[0x7b]	30203	1			T1	695		T2	390		T3	4
valid_sources[0x7c]	43868	1			T1	614		T2	480		T3	5
valid_sources[0x7d]	30872	1			T1	530		T2	380		T3	4
valid_sources[0x7e]	34639	1			T1	856		T2	403		T3	3
valid_sources[0x7f]	30726	1			T1	733		T2	445		T3	4
valid_sources[0x80]	32936	1			T1	708		T2	508		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1090691

1

T1

8590

T2

4488

T3

4

values[0x0]

all_enables

biggest_size

1685719

1

T1

27410

T2

15537

T3

431

values[0x1]

all_enables

biggest_size

1660649

1

T1

26755

T2

15324

T3

453