Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3792225

1

T1

105910

T2

59305

T3

4

full_word

4438509

1

T1

62755

T2

35349

T3

888

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8230364	1			T1	168665		T2	94654		T3	892
auto[TlIntgErrCmd]	120	1			T51	9		T82	5		T83	1
auto[TlIntgErrData]	124	1			T51	7		T82	5		T83	4
auto[TlIntgErrBoth]	126	1			T51	4		T82	10		T83	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4514089

1

T1

104387

T2

58298

T3

5

auto[1]

3716645

1

T1

64278

T2

36356

T3

887

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3422872	1			T1	95797		T2	53810		T3	1
auto[TlIntgErrNone]	partial	auto[1]	369019	1			T1	10113		T2	5495		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	1091051	1			T1	8590		T2	4488		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	3347422	1			T1	54165		T2	30861		T3	884
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T51	2		T82	2		T238	1
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T51	5		T82	3		T238	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T51	1		T92	2		T243	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T51	1		T83	1		T92	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T51	3		T82	1		T83	3
auto[TlIntgErrData]	partial	auto[1]	51	1			T51	2		T82	4		T238	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T51	2		T83	1		T241	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T238	1		T92	1		T241	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T82	4		T83	3		T238	1
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T51	4		T82	5		T83	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T240	1		T244	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T82	1		T92	1		T243	1