Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	607537438	3390732	0	0
gen_wmask[1].MaskCheckPortA_A	607537438	3390732	0	0
gen_wmask[2].MaskCheckPortA_A	607537438	3390732	0	0
gen_wmask[3].MaskCheckPortA_A	607537438	3390732	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607537438	3390732	0	0
T1	1080880	27016	0	0
T2	1284631	8724	0	0
T3	99330	832	0	0
T4	877089	9007	0	0
T5	2947	832	0	0
T6	204531	832	0	0
T7	1460	0	0	0
T8	419598	1880	0	0
T9	1398135	31051	0	0
T10	7422	832	0	0
T11	70929	832	0	0
T12	16581	0	0	0
T15	0	14185	0	0
T16	0	1506	0	0
T17	0	8794	0	0
T28	0	3365	0	0
T29	0	1318	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607537438	3390732	0	0
T1	1080880	27016	0	0
T2	1284631	8724	0	0
T3	99330	832	0	0
T4	877089	9007	0	0
T5	2947	832	0	0
T6	204531	832	0	0
T7	1460	0	0	0
T8	419598	1880	0	0
T9	1398135	31051	0	0
T10	7422	832	0	0
T11	70929	832	0	0
T12	16581	0	0	0
T15	0	14185	0	0
T16	0	1506	0	0
T17	0	8794	0	0
T28	0	3365	0	0
T29	0	1318	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607537438	3390732	0	0
T1	1080880	27016	0	0
T2	1284631	8724	0	0
T3	99330	832	0	0
T4	877089	9007	0	0
T5	2947	832	0	0
T6	204531	832	0	0
T7	1460	0	0	0
T8	419598	1880	0	0
T9	1398135	31051	0	0
T10	7422	832	0	0
T11	70929	832	0	0
T12	16581	0	0	0
T15	0	14185	0	0
T16	0	1506	0	0
T17	0	8794	0	0
T28	0	3365	0	0
T29	0	1318	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607537438	3390732	0	0
T1	1080880	27016	0	0
T2	1284631	8724	0	0
T3	99330	832	0	0
T4	877089	9007	0	0
T5	2947	832	0	0
T6	204531	832	0	0
T7	1460	0	0	0
T8	419598	1880	0	0
T9	1398135	31051	0	0
T10	7422	832	0	0
T11	70929	832	0	0
T12	16581	0	0	0
T15	0	14185	0	0
T16	0	1506	0	0
T17	0	8794	0	0
T28	0	3365	0	0
T29	0	1318	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	453194309	2157719	0	0
gen_wmask[1].MaskCheckPortA_A	453194309	2157719	0	0
gen_wmask[2].MaskCheckPortA_A	453194309	2157719	0	0
gen_wmask[3].MaskCheckPortA_A	453194309	2157719	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	2157719	0	0
T1	961172	15403	0	0
T2	570710	7142	0	0
T3	22474	832	0	0
T4	312344	3732	0	0
T5	2947	832	0	0
T6	182627	832	0	0
T7	1460	0	0	0
T8	373899	683	0	0
T9	507490	13240	0	0
T10	7222	832	0	0
T11	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	2157719	0	0
T1	961172	15403	0	0
T2	570710	7142	0	0
T3	22474	832	0	0
T4	312344	3732	0	0
T5	2947	832	0	0
T6	182627	832	0	0
T7	1460	0	0	0
T8	373899	683	0	0
T9	507490	13240	0	0
T10	7222	832	0	0
T11	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	2157719	0	0
T1	961172	15403	0	0
T2	570710	7142	0	0
T3	22474	832	0	0
T4	312344	3732	0	0
T5	2947	832	0	0
T6	182627	832	0	0
T7	1460	0	0	0
T8	373899	683	0	0
T9	507490	13240	0	0
T10	7222	832	0	0
T11	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	2157719	0	0
T1	961172	15403	0	0
T2	570710	7142	0	0
T3	22474	832	0	0
T4	312344	3732	0	0
T5	2947	832	0	0
T6	182627	832	0	0
T7	1460	0	0	0
T8	373899	683	0	0
T9	507490	13240	0	0
T10	7222	832	0	0
T11	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	154343129	1233013	0	0
gen_wmask[1].MaskCheckPortA_A	154343129	1233013	0	0
gen_wmask[2].MaskCheckPortA_A	154343129	1233013	0	0
gen_wmask[3].MaskCheckPortA_A	154343129	1233013	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	1233013	0	0
T1	119708	11613	0	0
T2	713921	1582	0	0
T3	76856	0	0	0
T4	564745	5275	0	0
T6	21904	0	0	0
T8	45699	1197	0	0
T9	890645	17811	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	14185	0	0
T16	0	1506	0	0
T17	0	8794	0	0
T28	0	3365	0	0
T29	0	1318	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	1233013	0	0
T1	119708	11613	0	0
T2	713921	1582	0	0
T3	76856	0	0	0
T4	564745	5275	0	0
T6	21904	0	0	0
T8	45699	1197	0	0
T9	890645	17811	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	14185	0	0
T16	0	1506	0	0
T17	0	8794	0	0
T28	0	3365	0	0
T29	0	1318	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	1233013	0	0
T1	119708	11613	0	0
T2	713921	1582	0	0
T3	76856	0	0	0
T4	564745	5275	0	0
T6	21904	0	0	0
T8	45699	1197	0	0
T9	890645	17811	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	14185	0	0
T16	0	1506	0	0
T17	0	8794	0	0
T28	0	3365	0	0
T29	0	1318	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	1233013	0	0
T1	119708	11613	0	0
T2	713921	1582	0	0
T3	76856	0	0	0
T4	564745	5275	0	0
T6	21904	0	0	0
T8	45699	1197	0	0
T9	890645	17811	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	14185	0	0
T16	0	1506	0	0
T17	0	8794	0	0
T28	0	3365	0	0
T29	0	1318	0	0