Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455444363	2974588	0	0
DepthKnown_A	455444363	455315373	0	0
RvalidKnown_A	455444363	455315373	0	0
WreadyKnown_A	455444363	455315373	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	2974588	0	0
T1	961172	16654	0	0
T2	570710	8320	0	0
T3	22474	1668	0	0
T4	312344	3327	0	0
T5	2947	1663	0	0
T6	182627	832	0	0
T7	1460	0	0	0
T8	373899	0	0	0
T9	507490	17474	0	0
T10	7222	832	0	0
T11	0	1663	0	0
T12	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455444363	3240765	0	0
DepthKnown_A	455444363	455315373	0	0
RvalidKnown_A	455444363	455315373	0	0
WreadyKnown_A	455444363	455315373	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	3240765	0	0
T1	961172	49518	0	0
T2	570710	16864	0	0
T3	22474	837	0	0
T4	312344	2496	0	0
T5	2947	832	0	0
T6	182627	832	0	0
T7	1460	0	0	0
T8	373899	0	0	0
T9	507490	32859	0	0
T10	7222	832	0	0
T11	0	832	0	0
T12	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455444363	195929	0	0
DepthKnown_A	455444363	455315373	0	0
RvalidKnown_A	455444363	455315373	0	0
WreadyKnown_A	455444363	455315373	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	195929	0	0
T1	961172	2061	0	0
T2	570710	340	0	0
T3	22474	0	0	0
T4	312344	722	0	0
T5	2947	0	0	0
T6	182627	0	0	0
T7	1460	0	0	0
T8	373899	311	0	0
T9	507490	1982	0	0
T10	7222	0	0	0
T15	0	1728	0	0
T16	0	432	0	0
T17	0	438	0	0
T28	0	192	0	0
T29	0	321	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455444363	434938	0	0
DepthKnown_A	455444363	455315373	0	0
RvalidKnown_A	455444363	455315373	0	0
WreadyKnown_A	455444363	455315373	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	434938	0	0
T1	961172	9187	0	0
T2	570710	1098	0	0
T3	22474	0	0	0
T4	312344	722	0	0
T5	2947	0	0	0
T6	182627	0	0	0
T7	1460	0	0	0
T8	373899	311	0	0
T9	507490	8950	0	0
T10	7222	0	0	0
T15	0	1717	0	0
T16	0	1801	0	0
T17	0	438	0	0
T28	0	192	0	0
T29	0	1495	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455444363	6479399	0	0
DepthKnown_A	455444363	455315373	0	0
RvalidKnown_A	455444363	455315373	0	0
WreadyKnown_A	455444363	455315373	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	6479399	0	0
T1	961172	170024	0	0
T2	570710	92685	0	0
T3	22474	60	0	0
T4	312344	8588	0	0
T5	2947	44	0	0
T6	182627	9765	0	0
T7	1460	45	0	0
T8	373899	6407	0	0
T9	507490	11977	0	0
T10	7222	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455444363	14076533	0	0
DepthKnown_A	455444363	455315373	0	0
RvalidKnown_A	455444363	455315373	0	0
WreadyKnown_A	455444363	455315373	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	14076533	0	0
T1	961172	678214	0	0
T2	570710	272318	0	0
T3	22474	312	0	0
T4	312344	8530	0	0
T5	2947	44	0	0
T6	182627	9764	0	0
T7	1460	45	0	0
T8	373899	6385	0	0
T9	507490	47346	0	0
T10	7222	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455444363	455315373	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0