Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	761880567	606102351	0	0
CheckNGreaterZero_A	2865	2865	0	0
GntImpliesReady_A	761880567	3782065	0	0
GntImpliesValid_A	761880567	3782065	0	0
GrantKnown_A	761880567	606102351	0	0
IdxKnown_A	761880567	606102351	0	0
IndexIsCorrect_A	761880567	3782065	0	0
LockArbDecision_A	761880567	0	0	0
NoReadyValidNoGrant_A	761880567	0	0	0
ReadyAndValidImplyGrant_A	761880567	3782065	0	0
ReqAndReadyImplyGrant_A	761880567	3782065	0	0
ReqImpliesValid_A	761880567	3782065	0	0
ReqStaysHighUntilGranted0_M	761880567	0	0	0
RoundRobin_A	761880567	5	0	955
ValidKnown_A	761880567	606102351	0	0
gen_data_port_assertion.DataFlow_A	761880567	3782065	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761880567	606102351	0	0
T1	1200588	2144227	0	0
T2	1998552	1281564	0	0
T3	176186	99255	0	0
T4	1441834	872493	0	0
T5	2947	2876	0	0
T6	226435	204433	0	0
T7	1460	1382	0	0
T8	465297	417200	0	0
T9	2288780	1388400	0	0
T10	7622	7343	0	0
T11	141858	70224	0	0
T12	33162	16183	0	0
T13	0	8304	0	0
T15	0	402136	0	0
T16	0	66352	0	0
T17	0	25160	0	0
T23	0	53840	0	0
T24	0	2952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2865	2865	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761880567	3782065	0	0
T1	1200588	31406	0	0
T2	1998552	9592	0	0
T3	176186	832	0	0
T4	1441834	11097	0	0
T5	2947	832	0	0
T6	226435	832	0	0
T7	1460	0	0	0
T8	465297	2932	0	0
T9	2288780	34742	0	0
T10	7622	832	0	0
T11	141858	832	0	0
T12	33162	0	0	0
T15	0	15413	0	0
T16	0	2062	0	0
T17	0	8921	0	0
T24	0	163	0	0
T28	0	3365	0	0
T29	0	1318	0	0
T35	0	5090	0	0
T36	0	859	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761880567	3782065	0	0
T1	1200588	31406	0	0
T2	1998552	9592	0	0
T3	176186	832	0	0
T4	1441834	11097	0	0
T5	2947	832	0	0
T6	226435	832	0	0
T7	1460	0	0	0
T8	465297	2932	0	0
T9	2288780	34742	0	0
T10	7622	832	0	0
T11	141858	832	0	0
T12	33162	0	0	0
T15	0	15413	0	0
T16	0	2062	0	0
T17	0	8921	0	0
T24	0	163	0	0
T28	0	3365	0	0
T29	0	1318	0	0
T35	0	5090	0	0
T36	0	859	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761880567	606102351	0	0
T1	1200588	2144227	0	0
T2	1998552	1281564	0	0
T3	176186	99255	0	0
T4	1441834	872493	0	0
T5	2947	2876	0	0
T6	226435	204433	0	0
T7	1460	1382	0	0
T8	465297	417200	0	0
T9	2288780	1388400	0	0
T10	7622	7343	0	0
T11	141858	70224	0	0
T12	33162	16183	0	0
T13	0	8304	0	0
T15	0	402136	0	0
T16	0	66352	0	0
T17	0	25160	0	0
T23	0	53840	0	0
T24	0	2952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761880567	606102351	0	0
T1	1200588	2144227	0	0
T2	1998552	1281564	0	0
T3	176186	99255	0	0
T4	1441834	872493	0	0
T5	2947	2876	0	0
T6	226435	204433	0	0
T7	1460	1382	0	0
T8	465297	417200	0	0
T9	2288780	1388400	0	0
T10	7622	7343	0	0
T11	141858	70224	0	0
T12	33162	16183	0	0
T13	0	8304	0	0
T15	0	402136	0	0
T16	0	66352	0	0
T17	0	25160	0	0
T23	0	53840	0	0
T24	0	2952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761880567	3782065	0	0
T1	1200588	31406	0	0
T2	1998552	9592	0	0
T3	176186	832	0	0
T4	1441834	11097	0	0
T5	2947	832	0	0
T6	226435	832	0	0
T7	1460	0	0	0
T8	465297	2932	0	0
T9	2288780	34742	0	0
T10	7622	832	0	0
T11	141858	832	0	0
T12	33162	0	0	0
T15	0	15413	0	0
T16	0	2062	0	0
T17	0	8921	0	0
T24	0	163	0	0
T28	0	3365	0	0
T29	0	1318	0	0
T35	0	5090	0	0
T36	0	859	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761880567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761880567	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761880567	3782065	0	0
T1	1200588	31406	0	0
T2	1998552	9592	0	0
T3	176186	832	0	0
T4	1441834	11097	0	0
T5	2947	832	0	0
T6	226435	832	0	0
T7	1460	0	0	0
T8	465297	2932	0	0
T9	2288780	34742	0	0
T10	7622	832	0	0
T11	141858	832	0	0
T12	33162	0	0	0
T15	0	15413	0	0
T16	0	2062	0	0
T17	0	8921	0	0
T24	0	163	0	0
T28	0	3365	0	0
T29	0	1318	0	0
T35	0	5090	0	0
T36	0	859	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761880567	3782065	0	0
T1	1200588	31406	0	0
T2	1998552	9592	0	0
T3	176186	832	0	0
T4	1441834	11097	0	0
T5	2947	832	0	0
T6	226435	832	0	0
T7	1460	0	0	0
T8	465297	2932	0	0
T9	2288780	34742	0	0
T10	7622	832	0	0
T11	141858	832	0	0
T12	33162	0	0	0
T15	0	15413	0	0
T16	0	2062	0	0
T17	0	8921	0	0
T24	0	163	0	0
T28	0	3365	0	0
T29	0	1318	0	0
T35	0	5090	0	0
T36	0	859	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761880567	3782065	0	0
T1	1200588	31406	0	0
T2	1998552	9592	0	0
T3	176186	832	0	0
T4	1441834	11097	0	0
T5	2947	832	0	0
T6	226435	832	0	0
T7	1460	0	0	0
T8	465297	2932	0	0
T9	2288780	34742	0	0
T10	7622	832	0	0
T11	141858	832	0	0
T12	33162	0	0	0
T15	0	15413	0	0
T16	0	2062	0	0
T17	0	8921	0	0
T24	0	163	0	0
T28	0	3365	0	0
T29	0	1318	0	0
T35	0	5090	0	0
T36	0	859	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	761880567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761880567	5	0	955
T18	114023	1	0	1
T19	110442	0	0	1
T34	281053	0	0	1
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	1312	0	0	1
T42	203874	0	0	1
T43	1052	0	0	1
T44	14206	0	0	1
T45	10082	0	0	1
T46	1284	0	0	1
T47	122446	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761880567	606102351	0	0
T1	1200588	2144227	0	0
T2	1998552	1281564	0	0
T3	176186	99255	0	0
T4	1441834	872493	0	0
T5	2947	2876	0	0
T6	226435	204433	0	0
T7	1460	1382	0	0
T8	465297	417200	0	0
T9	2288780	1388400	0	0
T10	7622	7343	0	0
T11	141858	70224	0	0
T12	33162	16183	0	0
T13	0	8304	0	0
T15	0	402136	0	0
T16	0	66352	0	0
T17	0	25160	0	0
T23	0	53840	0	0
T24	0	2952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761880567	3782065	0	0
T1	1200588	31406	0	0
T2	1998552	9592	0	0
T3	176186	832	0	0
T4	1441834	11097	0	0
T5	2947	832	0	0
T6	226435	832	0	0
T7	1460	0	0	0
T8	465297	2932	0	0
T9	2288780	34742	0	0
T10	7622	832	0	0
T11	141858	832	0	0
T12	33162	0	0	0
T15	0	15413	0	0
T16	0	2062	0	0
T17	0	8921	0	0
T24	0	163	0	0
T28	0	3365	0	0
T29	0	1318	0	0
T35	0	5090	0	0
T36	0	859	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	154343129	29447429	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	154343129	639858	0	0
GntImpliesValid_A	154343129	639858	0	0
GrantKnown_A	154343129	29447429	0	0
IdxKnown_A	154343129	29447429	0	0
IndexIsCorrect_A	154343129	639858	0	0
LockArbDecision_A	154343129	0	0	0
NoReadyValidNoGrant_A	154343129	0	0	0
ReadyAndValidImplyGrant_A	154343129	639858	0	0
ReqAndReadyImplyGrant_A	154343129	639858	0	0
ReqImpliesValid_A	154343129	639858	0	0
ReqStaysHighUntilGranted0_M	154343129	0	0	0
RoundRobin_A	154343129	0	0	0
ValidKnown_A	154343129	29447429	0	0
gen_data_port_assertion.DataFlow_A	154343129	639858	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	29447429	0	0
T1	119708	185296	0	0
T2	713921	38408	0	0
T3	76856	0	0	0
T4	564745	200336	0	0
T6	21904	0	0	0
T8	45699	43352	0	0
T9	890645	351704	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	402136	0	0
T16	0	66352	0	0
T17	0	25160	0	0
T23	0	53840	0	0
T24	0	2952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	639858	0	0
T1	119708	8040	0	0
T2	713921	1583	0	0
T3	76856	0	0	0
T4	564745	3530	0	0
T6	21904	0	0	0
T8	45699	1938	0	0
T9	890645	5301	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	4236	0	0
T16	0	1433	0	0
T17	0	447	0	0
T24	0	163	0	0
T35	0	5090	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	639858	0	0
T1	119708	8040	0	0
T2	713921	1583	0	0
T3	76856	0	0	0
T4	564745	3530	0	0
T6	21904	0	0	0
T8	45699	1938	0	0
T9	890645	5301	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	4236	0	0
T16	0	1433	0	0
T17	0	447	0	0
T24	0	163	0	0
T35	0	5090	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	29447429	0	0
T1	119708	185296	0	0
T2	713921	38408	0	0
T3	76856	0	0	0
T4	564745	200336	0	0
T6	21904	0	0	0
T8	45699	43352	0	0
T9	890645	351704	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	402136	0	0
T16	0	66352	0	0
T17	0	25160	0	0
T23	0	53840	0	0
T24	0	2952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	29447429	0	0
T1	119708	185296	0	0
T2	713921	38408	0	0
T3	76856	0	0	0
T4	564745	200336	0	0
T6	21904	0	0	0
T8	45699	43352	0	0
T9	890645	351704	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	402136	0	0
T16	0	66352	0	0
T17	0	25160	0	0
T23	0	53840	0	0
T24	0	2952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	639858	0	0
T1	119708	8040	0	0
T2	713921	1583	0	0
T3	76856	0	0	0
T4	564745	3530	0	0
T6	21904	0	0	0
T8	45699	1938	0	0
T9	890645	5301	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	4236	0	0
T16	0	1433	0	0
T17	0	447	0	0
T24	0	163	0	0
T35	0	5090	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	639858	0	0
T1	119708	8040	0	0
T2	713921	1583	0	0
T3	76856	0	0	0
T4	564745	3530	0	0
T6	21904	0	0	0
T8	45699	1938	0	0
T9	890645	5301	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	4236	0	0
T16	0	1433	0	0
T17	0	447	0	0
T24	0	163	0	0
T35	0	5090	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	639858	0	0
T1	119708	8040	0	0
T2	713921	1583	0	0
T3	76856	0	0	0
T4	564745	3530	0	0
T6	21904	0	0	0
T8	45699	1938	0	0
T9	890645	5301	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	4236	0	0
T16	0	1433	0	0
T17	0	447	0	0
T24	0	163	0	0
T35	0	5090	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	639858	0	0
T1	119708	8040	0	0
T2	713921	1583	0	0
T3	76856	0	0	0
T4	564745	3530	0	0
T6	21904	0	0	0
T8	45699	1938	0	0
T9	890645	5301	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	4236	0	0
T16	0	1433	0	0
T17	0	447	0	0
T24	0	163	0	0
T35	0	5090	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	29447429	0	0
T1	119708	185296	0	0
T2	713921	38408	0	0
T3	76856	0	0	0
T4	564745	200336	0	0
T6	21904	0	0	0
T8	45699	43352	0	0
T9	890645	351704	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	402136	0	0
T16	0	66352	0	0
T17	0	25160	0	0
T23	0	53840	0	0
T24	0	2952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	639858	0	0
T1	119708	8040	0	0
T2	713921	1583	0	0
T3	76856	0	0	0
T4	564745	3530	0	0
T6	21904	0	0	0
T8	45699	1938	0	0
T9	890645	5301	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	4236	0	0
T16	0	1433	0	0
T17	0	447	0	0
T24	0	163	0	0
T35	0	5090	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	154343129	123547224	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	154343129	800525	0	0
GntImpliesValid_A	154343129	800525	0	0
GrantKnown_A	154343129	123547224	0	0
IdxKnown_A	154343129	123547224	0	0
IndexIsCorrect_A	154343129	800525	0	0
LockArbDecision_A	154343129	0	0	0
NoReadyValidNoGrant_A	154343129	0	0	0
ReadyAndValidImplyGrant_A	154343129	800525	0	0
ReqAndReadyImplyGrant_A	154343129	800525	0	0
ReqImpliesValid_A	154343129	800525	0	0
ReqStaysHighUntilGranted0_M	154343129	0	0	0
RoundRobin_A	154343129	0	0	0
ValidKnown_A	154343129	123547224	0	0
gen_data_port_assertion.DataFlow_A	154343129	800525	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	123547224	0	0
T1	119708	997790	0	0
T2	713921	672456	0	0
T3	76856	76856	0	0
T4	564745	360198	0	0
T6	21904	21904	0	0
T8	45699	0	0	0
T9	890645	529369	0	0
T10	200	200	0	0
T11	70929	70224	0	0
T12	16581	16183	0	0
T13	0	8304	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	800525	0	0
T1	119708	5876	0	0
T2	713921	522	0	0
T3	76856	0	0	0
T4	564745	3107	0	0
T6	21904	0	0	0
T8	45699	0	0	0
T9	890645	14250	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	11177	0	0
T16	0	629	0	0
T17	0	8474	0	0
T28	0	3365	0	0
T29	0	1318	0	0
T36	0	859	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	800525	0	0
T1	119708	5876	0	0
T2	713921	522	0	0
T3	76856	0	0	0
T4	564745	3107	0	0
T6	21904	0	0	0
T8	45699	0	0	0
T9	890645	14250	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	11177	0	0
T16	0	629	0	0
T17	0	8474	0	0
T28	0	3365	0	0
T29	0	1318	0	0
T36	0	859	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	123547224	0	0
T1	119708	997790	0	0
T2	713921	672456	0	0
T3	76856	76856	0	0
T4	564745	360198	0	0
T6	21904	21904	0	0
T8	45699	0	0	0
T9	890645	529369	0	0
T10	200	200	0	0
T11	70929	70224	0	0
T12	16581	16183	0	0
T13	0	8304	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	123547224	0	0
T1	119708	997790	0	0
T2	713921	672456	0	0
T3	76856	76856	0	0
T4	564745	360198	0	0
T6	21904	21904	0	0
T8	45699	0	0	0
T9	890645	529369	0	0
T10	200	200	0	0
T11	70929	70224	0	0
T12	16581	16183	0	0
T13	0	8304	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	800525	0	0
T1	119708	5876	0	0
T2	713921	522	0	0
T3	76856	0	0	0
T4	564745	3107	0	0
T6	21904	0	0	0
T8	45699	0	0	0
T9	890645	14250	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	11177	0	0
T16	0	629	0	0
T17	0	8474	0	0
T28	0	3365	0	0
T29	0	1318	0	0
T36	0	859	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	800525	0	0
T1	119708	5876	0	0
T2	713921	522	0	0
T3	76856	0	0	0
T4	564745	3107	0	0
T6	21904	0	0	0
T8	45699	0	0	0
T9	890645	14250	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	11177	0	0
T16	0	629	0	0
T17	0	8474	0	0
T28	0	3365	0	0
T29	0	1318	0	0
T36	0	859	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	800525	0	0
T1	119708	5876	0	0
T2	713921	522	0	0
T3	76856	0	0	0
T4	564745	3107	0	0
T6	21904	0	0	0
T8	45699	0	0	0
T9	890645	14250	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	11177	0	0
T16	0	629	0	0
T17	0	8474	0	0
T28	0	3365	0	0
T29	0	1318	0	0
T36	0	859	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	800525	0	0
T1	119708	5876	0	0
T2	713921	522	0	0
T3	76856	0	0	0
T4	564745	3107	0	0
T6	21904	0	0	0
T8	45699	0	0	0
T9	890645	14250	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	11177	0	0
T16	0	629	0	0
T17	0	8474	0	0
T28	0	3365	0	0
T29	0	1318	0	0
T36	0	859	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	123547224	0	0
T1	119708	997790	0	0
T2	713921	672456	0	0
T3	76856	76856	0	0
T4	564745	360198	0	0
T6	21904	21904	0	0
T8	45699	0	0	0
T9	890645	529369	0	0
T10	200	200	0	0
T11	70929	70224	0	0
T12	16581	16183	0	0
T13	0	8304	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154343129	800525	0	0
T1	119708	5876	0	0
T2	713921	522	0	0
T3	76856	0	0	0
T4	564745	3107	0	0
T6	21904	0	0	0
T8	45699	0	0	0
T9	890645	14250	0	0
T10	200	0	0	0
T11	70929	0	0	0
T12	16581	0	0	0
T15	0	11177	0	0
T16	0	629	0	0
T17	0	8474	0	0
T28	0	3365	0	0
T29	0	1318	0	0
T36	0	859	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453194309	453107698	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	453194309	2341682	0	0
GntImpliesValid_A	453194309	2341682	0	0
GrantKnown_A	453194309	453107698	0	0
IdxKnown_A	453194309	453107698	0	0
IndexIsCorrect_A	453194309	2341682	0	0
LockArbDecision_A	453194309	0	0	0
NoReadyValidNoGrant_A	453194309	0	0	0
ReadyAndValidImplyGrant_A	453194309	2341682	0	0
ReqAndReadyImplyGrant_A	453194309	2341682	0	0
ReqImpliesValid_A	453194309	2341682	0	0
ReqStaysHighUntilGranted0_M	453194309	0	0	0
RoundRobin_A	453194309	5	0	955
ValidKnown_A	453194309	453107698	0	0
gen_data_port_assertion.DataFlow_A	453194309	2341682	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	453107698	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	2341682	0	0
T1	961172	17490	0	0
T2	570710	7487	0	0
T3	22474	832	0	0
T4	312344	4460	0	0
T5	2947	832	0	0
T6	182627	832	0	0
T7	1460	0	0	0
T8	373899	994	0	0
T9	507490	15191	0	0
T10	7222	832	0	0
T11	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	2341682	0	0
T1	961172	17490	0	0
T2	570710	7487	0	0
T3	22474	832	0	0
T4	312344	4460	0	0
T5	2947	832	0	0
T6	182627	832	0	0
T7	1460	0	0	0
T8	373899	994	0	0
T9	507490	15191	0	0
T10	7222	832	0	0
T11	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	453107698	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	453107698	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	2341682	0	0
T1	961172	17490	0	0
T2	570710	7487	0	0
T3	22474	832	0	0
T4	312344	4460	0	0
T5	2947	832	0	0
T6	182627	832	0	0
T7	1460	0	0	0
T8	373899	994	0	0
T9	507490	15191	0	0
T10	7222	832	0	0
T11	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	2341682	0	0
T1	961172	17490	0	0
T2	570710	7487	0	0
T3	22474	832	0	0
T4	312344	4460	0	0
T5	2947	832	0	0
T6	182627	832	0	0
T7	1460	0	0	0
T8	373899	994	0	0
T9	507490	15191	0	0
T10	7222	832	0	0
T11	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	2341682	0	0
T1	961172	17490	0	0
T2	570710	7487	0	0
T3	22474	832	0	0
T4	312344	4460	0	0
T5	2947	832	0	0
T6	182627	832	0	0
T7	1460	0	0	0
T8	373899	994	0	0
T9	507490	15191	0	0
T10	7222	832	0	0
T11	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	2341682	0	0
T1	961172	17490	0	0
T2	570710	7487	0	0
T3	22474	832	0	0
T4	312344	4460	0	0
T5	2947	832	0	0
T6	182627	832	0	0
T7	1460	0	0	0
T8	373899	994	0	0
T9	507490	15191	0	0
T10	7222	832	0	0
T11	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	5	0	955
T18	114023	1	0	1
T19	110442	0	0	1
T34	281053	0	0	1
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	1312	0	0	1
T42	203874	0	0	1
T43	1052	0	0	1
T44	14206	0	0	1
T45	10082	0	0	1
T46	1284	0	0	1
T47	122446	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	453107698	0	0
T1	961172	961141	0	0
T2	570710	570700	0	0
T3	22474	22399	0	0
T4	312344	311959	0	0
T5	2947	2876	0	0
T6	182627	182529	0	0
T7	1460	1382	0	0
T8	373899	373848	0	0
T9	507490	507327	0	0
T10	7222	7143	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453194309	2341682	0	0
T1	961172	17490	0	0
T2	570710	7487	0	0
T3	22474	832	0	0
T4	312344	4460	0	0
T5	2947	832	0	0
T6	182627	832	0	0
T7	1460	0	0	0
T8	373899	994	0	0
T9	507490	15191	0	0
T10	7222	832	0	0
T11	0	832	0	0