Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3488849	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4260941

1

T1

15190

T2

25897

T3

7685

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4181739	1			T1	26869		T2	33656		T3	2423
values[0x0]	1784367	1			T1	7712		T2	12405		T3	3106
values[0x1]	1783684	1			T1	7699		T2	12378		T3	3076

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2472457	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5277333

1

T1

23901

T2

36065

T3

7886

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29121	1			T1	154		T2	267		T3	33
valid_sources[0x01]	31521	1			T1	119		T2	207		T3	31
valid_sources[0x02]	38313	1			T1	218		T2	249		T3	23
valid_sources[0x03]	33317	1			T1	200		T2	219		T3	27
valid_sources[0x04]	27428	1			T1	81		T2	227		T3	26
valid_sources[0x05]	32636	1			T1	142		T2	220		T3	27
valid_sources[0x06]	32452	1			T1	122		T2	231		T3	37
valid_sources[0x07]	27519	1			T1	294		T2	186		T3	26
valid_sources[0x08]	28920	1			T1	99		T2	242		T3	13
valid_sources[0x09]	27279	1			T1	99		T2	279		T3	25
valid_sources[0x0a]	26957	1			T1	169		T2	233		T3	36
valid_sources[0x0b]	31239	1			T1	183		T2	217		T3	36
valid_sources[0x0c]	28932	1			T1	248		T2	196		T3	29
valid_sources[0x0d]	29482	1			T1	79		T2	196		T3	22
valid_sources[0x0e]	29941	1			T1	101		T2	259		T3	29
valid_sources[0x0f]	29705	1			T1	201		T2	200		T3	18
valid_sources[0x10]	31137	1			T1	149		T2	220		T3	32
valid_sources[0x11]	30588	1			T1	109		T2	222		T3	28
valid_sources[0x12]	28889	1			T1	129		T2	261		T3	23
valid_sources[0x13]	27801	1			T1	231		T2	276		T3	59
valid_sources[0x14]	30599	1			T1	216		T2	200		T3	41
valid_sources[0x15]	27766	1			T1	148		T2	198		T3	20
valid_sources[0x16]	29472	1			T1	89		T2	212		T3	40
valid_sources[0x17]	27349	1			T1	201		T2	246		T3	23
valid_sources[0x18]	31208	1			T1	246		T2	254		T3	28
valid_sources[0x19]	32780	1			T1	158		T2	197		T3	19
valid_sources[0x1a]	31872	1			T1	150		T2	254		T3	45
valid_sources[0x1b]	31444	1			T1	69		T2	240		T3	27
valid_sources[0x1c]	33274	1			T1	113		T2	210		T3	33
valid_sources[0x1d]	31676	1			T1	69		T2	254		T3	33
valid_sources[0x1e]	32087	1			T1	234		T2	255		T3	36
valid_sources[0x1f]	28572	1			T1	123		T2	185		T3	26
valid_sources[0x20]	27795	1			T1	188		T2	224		T3	16
valid_sources[0x21]	27578	1			T1	114		T2	227		T3	25
valid_sources[0x22]	29230	1			T1	186		T2	208		T3	28
valid_sources[0x23]	28480	1			T1	195		T2	194		T3	39
valid_sources[0x24]	28243	1			T1	128		T2	226		T3	29
valid_sources[0x25]	32025	1			T1	285		T2	231		T3	30
valid_sources[0x26]	30007	1			T1	98		T2	232		T3	30
valid_sources[0x27]	30481	1			T1	201		T2	268		T3	40
valid_sources[0x28]	27854	1			T1	113		T2	245		T3	50
valid_sources[0x29]	30726	1			T1	126		T2	211		T3	32
valid_sources[0x2a]	29407	1			T1	67		T2	181		T3	50
valid_sources[0x2b]	28469	1			T1	99		T2	199		T3	67
valid_sources[0x2c]	63140	1			T1	186		T2	246		T3	27
valid_sources[0x2d]	35631	1			T1	141		T2	273		T3	38
valid_sources[0x2e]	29201	1			T1	266		T2	245		T3	27
valid_sources[0x2f]	29070	1			T1	264		T2	210		T3	35
valid_sources[0x30]	29826	1			T1	92		T2	239		T3	46
valid_sources[0x31]	28774	1			T1	101		T2	227		T3	32
valid_sources[0x32]	27976	1			T1	111		T2	281		T3	31
valid_sources[0x33]	27414	1			T1	229		T2	185		T3	24
valid_sources[0x34]	27886	1			T1	182		T2	229		T3	42
valid_sources[0x35]	29153	1			T1	233		T2	239		T3	42
valid_sources[0x36]	32010	1			T1	185		T2	185		T3	42
valid_sources[0x37]	32396	1			T1	190		T2	248		T3	32
valid_sources[0x38]	28947	1			T1	262		T2	191		T3	20
valid_sources[0x39]	27045	1			T1	161		T2	249		T3	44
valid_sources[0x3a]	27540	1			T1	95		T2	247		T3	44
valid_sources[0x3b]	32369	1			T1	114		T2	247		T3	49
valid_sources[0x3c]	31510	1			T1	191		T2	233		T3	24
valid_sources[0x3d]	28514	1			T1	78		T2	245		T3	30
valid_sources[0x3e]	30396	1			T1	150		T2	218		T3	31
valid_sources[0x3f]	28670	1			T1	144		T2	233		T3	23
valid_sources[0x40]	31097	1			T1	280		T2	216		T3	34
valid_sources[0x41]	28080	1			T1	148		T2	220		T3	46
valid_sources[0x42]	29993	1			T1	181		T2	214		T3	43
valid_sources[0x43]	32549	1			T1	167		T2	230		T3	36
valid_sources[0x44]	28978	1			T1	98		T2	275		T3	32
valid_sources[0x45]	30325	1			T1	204		T2	260		T3	30
valid_sources[0x46]	31357	1			T1	267		T2	240		T3	39
valid_sources[0x47]	26577	1			T1	204		T2	253		T3	44
valid_sources[0x48]	29116	1			T1	185		T2	203		T3	28
valid_sources[0x49]	28856	1			T1	148		T2	214		T3	30
valid_sources[0x4a]	28783	1			T1	100		T2	265		T3	28
valid_sources[0x4b]	28508	1			T1	236		T2	228		T3	36
valid_sources[0x4c]	28533	1			T1	128		T2	255		T3	17
valid_sources[0x4d]	29615	1			T1	109		T2	225		T3	31
valid_sources[0x4e]	28717	1			T1	200		T2	251		T3	60
valid_sources[0x4f]	28275	1			T1	171		T2	241		T3	25
valid_sources[0x50]	27564	1			T1	241		T2	215		T3	19
valid_sources[0x51]	34853	1			T1	171		T2	225		T3	33
valid_sources[0x52]	29773	1			T1	107		T2	254		T3	38
valid_sources[0x53]	29482	1			T1	221		T2	212		T3	33
valid_sources[0x54]	30546	1			T1	146		T2	256		T3	50
valid_sources[0x55]	36827	1			T1	217		T2	201		T3	25
valid_sources[0x56]	28592	1			T1	134		T2	207		T3	28
valid_sources[0x57]	31639	1			T1	138		T2	208		T3	38
valid_sources[0x58]	32454	1			T1	175		T2	219		T3	25
valid_sources[0x59]	30793	1			T1	102		T2	178		T3	46
valid_sources[0x5a]	32809	1			T1	170		T2	247		T3	41
valid_sources[0x5b]	27759	1			T1	147		T2	211		T3	38
valid_sources[0x5c]	30887	1			T1	127		T2	237		T3	28
valid_sources[0x5d]	28287	1			T1	118		T2	263		T3	48
valid_sources[0x5e]	29626	1			T1	187		T2	187		T3	39
valid_sources[0x5f]	28855	1			T1	123		T2	208		T3	35
valid_sources[0x60]	28146	1			T1	195		T2	194		T3	42
valid_sources[0x61]	32022	1			T1	156		T2	229		T3	14
valid_sources[0x62]	39307	1			T1	173		T2	218		T3	39
valid_sources[0x63]	27627	1			T1	214		T2	209		T3	26
valid_sources[0x64]	28447	1			T1	66		T2	241		T3	27
valid_sources[0x65]	28430	1			T1	195		T2	212		T3	30
valid_sources[0x66]	30677	1			T1	180		T2	240		T3	27
valid_sources[0x67]	29507	1			T1	311		T2	271		T3	26
valid_sources[0x68]	28188	1			T1	219		T2	223		T3	71
valid_sources[0x69]	28185	1			T1	81		T2	232		T3	23
valid_sources[0x6a]	26439	1			T1	105		T2	217		T3	31
valid_sources[0x6b]	28126	1			T1	119		T2	205		T3	42
valid_sources[0x6c]	32545	1			T1	125		T2	227		T3	38
valid_sources[0x6d]	29134	1			T1	198		T2	239		T3	34
valid_sources[0x6e]	28886	1			T1	147		T2	239		T3	35
valid_sources[0x6f]	29418	1			T1	164		T2	195		T3	33
valid_sources[0x70]	28093	1			T1	126		T2	211		T3	28
valid_sources[0x71]	29009	1			T1	211		T2	241		T3	39
valid_sources[0x72]	29935	1			T1	166		T2	218		T3	53
valid_sources[0x73]	31496	1			T1	115		T2	210		T3	35
valid_sources[0x74]	29563	1			T1	154		T2	247		T3	30
valid_sources[0x75]	29265	1			T1	80		T2	209		T3	38
valid_sources[0x76]	33777	1			T1	194		T2	260		T3	39
valid_sources[0x77]	30164	1			T1	106		T2	204		T3	38
valid_sources[0x78]	26754	1			T1	90		T2	265		T3	27
valid_sources[0x79]	31105	1			T1	270		T2	196		T3	36
valid_sources[0x7a]	29590	1			T1	232		T2	235		T3	16
valid_sources[0x7b]	27932	1			T1	180		T2	205		T3	42
valid_sources[0x7c]	29516	1			T1	193		T2	262		T3	25
valid_sources[0x7d]	31198	1			T1	303		T2	202		T3	44
valid_sources[0x7e]	29283	1			T1	202		T2	228		T3	40
valid_sources[0x7f]	28066	1			T1	129		T2	239		T3	47
valid_sources[0x80]	31166	1			T1	166		T2	235		T3	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1014411

1

T1

2242

T2

4335

T3

1539

values[0x0]

all_enables

biggest_size

1635409

1

T1

6531

T2

10864

T3

3096

values[0x1]

all_enables

biggest_size

1611121

1

T1

6417

T2

10698

T3

3050