Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3510882

1

T1

27090

T2

32542

T3

920

full_word

4262228

1

T1

15190

T2

25897

T3

7685

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7772800	1			T1	42280		T2	58439		T3	8605
auto[TlIntgErrCmd]	108	1			T99	3		T100	7		T101	4
auto[TlIntgErrData]	99	1			T99	4		T100	5		T101	2
auto[TlIntgErrBoth]	103	1			T99	3		T100	8		T101	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4186772

1

T1

26869

T2

33656

T3

2423

auto[1]

3586338

1

T1

15411

T2

24783

T3

6182

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3171885	1			T1	24627		T2	29321		T3	884
auto[TlIntgErrNone]	partial	auto[1]	338707	1			T1	2463		T2	3221		T3	36
auto[TlIntgErrNone]	full_word	auto[0]	1014748	1			T1	2242		T2	4335		T3	1539
auto[TlIntgErrNone]	full_word	auto[1]	3247460	1			T1	12948		T2	21562		T3	6146
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T99	1		T100	2		T101	3
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T99	2		T100	5		T118	8
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T101	1		T187	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T164	1		T188	1		T189	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T99	2		T100	3		T101	1
auto[TlIntgErrData]	partial	auto[1]	46	1			T99	2		T100	2		T101	1
auto[TlIntgErrData]	full_word	auto[0]	1	1			T190	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T118	2		T164	1		T185	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T99	1		T100	2		T101	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T99	2		T100	6		T101	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T118	1		T191	1		T192	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T193	1		T187	1		T194	1