Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	651256615	3472418	0	0
gen_wmask[1].MaskCheckPortA_A	651256615	3472418	0	0
gen_wmask[2].MaskCheckPortA_A	651256615	3472418	0	0
gen_wmask[3].MaskCheckPortA_A	651256615	3472418	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651256615	3472418	0	0
T1	501983	11094	0	0
T2	1068529	17201	0	0
T3	652040	20054	0	0
T4	216902	832	0	0
T5	996329	7748	0	0
T6	1308	0	0	0
T7	345802	3766	0	0
T8	795084	12679	0	0
T9	4571	0	0	0
T10	908	0	0	0
T11	468515	8197	0	0
T12	289692	832	0	0
T13	0	12881	0	0
T23	0	832	0	0
T34	0	1171	0	0
T35	0	1032	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651256615	3472418	0	0
T1	501983	11094	0	0
T2	1068529	17201	0	0
T3	652040	20054	0	0
T4	216902	832	0	0
T5	996329	7748	0	0
T6	1308	0	0	0
T7	345802	3766	0	0
T8	795084	12679	0	0
T9	4571	0	0	0
T10	908	0	0	0
T11	468515	8197	0	0
T12	289692	832	0	0
T13	0	12881	0	0
T23	0	832	0	0
T34	0	1171	0	0
T35	0	1032	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651256615	3472418	0	0
T1	501983	11094	0	0
T2	1068529	17201	0	0
T3	652040	20054	0	0
T4	216902	832	0	0
T5	996329	7748	0	0
T6	1308	0	0	0
T7	345802	3766	0	0
T8	795084	12679	0	0
T9	4571	0	0	0
T10	908	0	0	0
T11	468515	8197	0	0
T12	289692	832	0	0
T13	0	12881	0	0
T23	0	832	0	0
T34	0	1171	0	0
T35	0	1032	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651256615	3472418	0	0
T1	501983	11094	0	0
T2	1068529	17201	0	0
T3	652040	20054	0	0
T4	216902	832	0	0
T5	996329	7748	0	0
T6	1308	0	0	0
T7	345802	3766	0	0
T8	795084	12679	0	0
T9	4571	0	0	0
T10	908	0	0	0
T11	468515	8197	0	0
T12	289692	832	0	0
T13	0	12881	0	0
T23	0	832	0	0
T34	0	1171	0	0
T35	0	1032	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	497991636	2161047	0	0
gen_wmask[1].MaskCheckPortA_A	497991636	2161047	0	0
gen_wmask[2].MaskCheckPortA_A	497991636	2161047	0	0
gen_wmask[3].MaskCheckPortA_A	497991636	2161047	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	2161047	0	0
T1	224337	5154	0	0
T2	443930	11684	0	0
T3	113868	5824	0	0
T4	192871	832	0	0
T5	334813	7488	0	0
T6	1308	0	0	0
T7	149596	869	0	0
T8	356477	6656	0	0
T9	3720	0	0	0
T10	908	0	0	0
T11	0	3344	0	0
T12	0	832	0	0
T23	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	2161047	0	0
T1	224337	5154	0	0
T2	443930	11684	0	0
T3	113868	5824	0	0
T4	192871	832	0	0
T5	334813	7488	0	0
T6	1308	0	0	0
T7	149596	869	0	0
T8	356477	6656	0	0
T9	3720	0	0	0
T10	908	0	0	0
T11	0	3344	0	0
T12	0	832	0	0
T23	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	2161047	0	0
T1	224337	5154	0	0
T2	443930	11684	0	0
T3	113868	5824	0	0
T4	192871	832	0	0
T5	334813	7488	0	0
T6	1308	0	0	0
T7	149596	869	0	0
T8	356477	6656	0	0
T9	3720	0	0	0
T10	908	0	0	0
T11	0	3344	0	0
T12	0	832	0	0
T23	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	2161047	0	0
T1	224337	5154	0	0
T2	443930	11684	0	0
T3	113868	5824	0	0
T4	192871	832	0	0
T5	334813	7488	0	0
T6	1308	0	0	0
T7	149596	869	0	0
T8	356477	6656	0	0
T9	3720	0	0	0
T10	908	0	0	0
T11	0	3344	0	0
T12	0	832	0	0
T23	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	153264979	1311371	0	0
gen_wmask[1].MaskCheckPortA_A	153264979	1311371	0	0
gen_wmask[2].MaskCheckPortA_A	153264979	1311371	0	0
gen_wmask[3].MaskCheckPortA_A	153264979	1311371	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	1311371	0	0
T1	277646	5940	0	0
T2	624599	5517	0	0
T3	538172	14230	0	0
T4	24031	0	0	0
T5	661516	260	0	0
T7	196206	2897	0	0
T8	438607	6023	0	0
T9	851	0	0	0
T11	468515	4853	0	0
T12	289692	0	0	0
T13	0	12881	0	0
T34	0	1171	0	0
T35	0	1032	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	1311371	0	0
T1	277646	5940	0	0
T2	624599	5517	0	0
T3	538172	14230	0	0
T4	24031	0	0	0
T5	661516	260	0	0
T7	196206	2897	0	0
T8	438607	6023	0	0
T9	851	0	0	0
T11	468515	4853	0	0
T12	289692	0	0	0
T13	0	12881	0	0
T34	0	1171	0	0
T35	0	1032	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	1311371	0	0
T1	277646	5940	0	0
T2	624599	5517	0	0
T3	538172	14230	0	0
T4	24031	0	0	0
T5	661516	260	0	0
T7	196206	2897	0	0
T8	438607	6023	0	0
T9	851	0	0	0
T11	468515	4853	0	0
T12	289692	0	0	0
T13	0	12881	0	0
T34	0	1171	0	0
T35	0	1032	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	1311371	0	0
T1	277646	5940	0	0
T2	624599	5517	0	0
T3	538172	14230	0	0
T4	24031	0	0	0
T5	661516	260	0	0
T7	196206	2897	0	0
T8	438607	6023	0	0
T9	851	0	0	0
T11	468515	4853	0	0
T12	289692	0	0	0
T13	0	12881	0	0
T34	0	1171	0	0
T35	0	1032	0	0