Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	499711834	3004446	0	0
DepthKnown_A	499711834	499586858	0	0
RvalidKnown_A	499711834	499586858	0	0
WreadyKnown_A	499711834	499586858	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	3004446	0	0
T1	224337	4998	0	0
T2	443930	16632	0	0
T3	113868	7486	0	0
T4	192871	1663	0	0
T5	334813	10812	0	0
T6	1308	0	0	0
T7	149596	0	0	0
T8	356477	7487	0	0
T9	3720	0	0	0
T10	908	0	0	0
T11	0	3327	0	0
T12	0	1669	0	0
T13	0	17477	0	0
T23	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	499711834	3400400	0	0
DepthKnown_A	499711834	499586858	0	0
RvalidKnown_A	499711834	499586858	0	0
WreadyKnown_A	499711834	499586858	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	3400400	0	0
T1	224337	9171	0	0
T2	443930	9984	0	0
T3	113868	5824	0	0
T4	192871	832	0	0
T5	334813	7488	0	0
T6	1308	0	0	0
T7	149596	0	0	0
T8	356477	20893	0	0
T9	3720	0	0	0
T10	908	0	0	0
T11	0	4263	0	0
T12	0	838	0	0
T13	0	23692	0	0
T23	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	499711834	188667	0	0
DepthKnown_A	499711834	499586858	0	0
RvalidKnown_A	499711834	499586858	0	0
WreadyKnown_A	499711834	499586858	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	188667	0	0
T1	224337	964	0	0
T2	443930	1340	0	0
T3	113868	610	0	0
T4	192871	0	0	0
T5	334813	64	0	0
T6	1308	0	0	0
T7	149596	750	0	0
T8	356477	321	0	0
T9	3720	0	0	0
T10	908	0	0	0
T11	0	625	0	0
T13	0	576	0	0
T34	0	97	0	0
T35	0	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	499711834	451474	0	0
DepthKnown_A	499711834	499586858	0	0
RvalidKnown_A	499711834	499586858	0	0
WreadyKnown_A	499711834	499586858	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	451474	0	0
T1	224337	4264	0	0
T2	443930	1340	0	0
T3	113868	610	0	0
T4	192871	0	0	0
T5	334813	64	0	0
T6	1308	0	0	0
T7	149596	2358	0	0
T8	356477	1424	0	0
T9	3720	0	0	0
T10	908	0	0	0
T11	0	1738	0	0
T13	0	1884	0	0
T34	0	97	0	0
T35	0	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	499711834	5960315	0	0
DepthKnown_A	499711834	499586858	0	0
RvalidKnown_A	499711834	499586858	0	0
WreadyKnown_A	499711834	499586858	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	5960315	0	0
T1	224337	41648	0	0
T2	443930	47356	0	0
T3	113868	2172	0	0
T4	192871	57	0	0
T5	334813	5284	0	0
T6	1308	49	0	0
T7	149596	4716	0	0
T8	356477	5694	0	0
T9	3720	32	0	0
T10	908	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	499711834	12523828	0	0
DepthKnown_A	499711834	499586858	0	0
RvalidKnown_A	499711834	499586858	0	0
WreadyKnown_A	499711834	499586858	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	12523828	0	0
T1	224337	168254	0	0
T2	443930	47115	0	0
T3	113868	2171	0	0
T4	192871	57	0	0
T5	334813	5283	0	0
T6	1308	49	0	0
T7	149596	13713	0	0
T8	356477	21266	0	0
T9	3720	142	0	0
T10	908	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499711834	499586858	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0