Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Unreachable
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	804521594	649846144	0	0
CheckNGreaterZero_A	2865	2865	0	0
GntImpliesReady_A	804521594	3851430	0	0
GntImpliesValid_A	804521594	3851430	0	0
GrantKnown_A	804521594	649846144	0	0
IdxKnown_A	804521594	649846144	0	0
IndexIsCorrect_A	804521594	3851430	0	0
LockArbDecision_A	804521594	0	0	0
NoReadyValidNoGrant_A	804521594	0	0	0
ReadyAndValidImplyGrant_A	804521594	3851430	0	0
ReqAndReadyImplyGrant_A	804521594	3851430	0	0
ReqImpliesValid_A	804521594	3851430	0	0
ReqStaysHighUntilGranted0_M	804521594	0	0	0
RoundRobin_A	804521594	11	0	955
ValidKnown_A	804521594	649846144	0	0
gen_data_port_assertion.DataFlow_A	804521594	3851430	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804521594	649846144	0	0
T1	779629	496111	0	0
T2	1693128	1059253	0	0
T3	1190212	650827	0	0
T4	240933	216374	0	0
T5	1657845	994210	0	0
T6	1308	1219	0	0
T7	542008	340939	0	0
T8	1233691	793374	0	0
T9	5422	4356	0	0
T10	908	811	0	0
T11	937030	464592	0	0
T12	579384	289692	0	0
T13	0	120395	0	0
T14	0	127824	0	0
T24	0	98784	0	0
T25	0	114472	0	0
T27	0	80368	0	0
T28	0	720	0	0
T29	0	111168	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2865	2865	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804521594	3851430	0	0
T1	779629	14051	0	0
T2	1693128	20433	0	0
T3	1190212	20684	0	0
T4	240933	832	0	0
T5	1657845	7816	0	0
T6	1308	0	0	0
T7	542008	5453	0	0
T8	1233691	13014	0	0
T9	5422	0	0	0
T10	908	0	0	0
T11	937030	9763	0	0
T12	579384	832	0	0
T13	0	12881	0	0
T15	0	9079	0	0
T23	0	832	0	0
T25	0	7180	0	0
T29	0	4542	0	0
T34	0	1171	0	0
T35	0	1032	0	0
T42	0	3095	0	0
T43	0	4224	0	0
T44	0	1543	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804521594	3851430	0	0
T1	779629	14051	0	0
T2	1693128	20433	0	0
T3	1190212	20684	0	0
T4	240933	832	0	0
T5	1657845	7816	0	0
T6	1308	0	0	0
T7	542008	5453	0	0
T8	1233691	13014	0	0
T9	5422	0	0	0
T10	908	0	0	0
T11	937030	9763	0	0
T12	579384	832	0	0
T13	0	12881	0	0
T15	0	9079	0	0
T23	0	832	0	0
T25	0	7180	0	0
T29	0	4542	0	0
T34	0	1171	0	0
T35	0	1032	0	0
T42	0	3095	0	0
T43	0	4224	0	0
T44	0	1543	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804521594	649846144	0	0
T1	779629	496111	0	0
T2	1693128	1059253	0	0
T3	1190212	650827	0	0
T4	240933	216374	0	0
T5	1657845	994210	0	0
T6	1308	1219	0	0
T7	542008	340939	0	0
T8	1233691	793374	0	0
T9	5422	4356	0	0
T10	908	811	0	0
T11	937030	464592	0	0
T12	579384	289692	0	0
T13	0	120395	0	0
T14	0	127824	0	0
T24	0	98784	0	0
T25	0	114472	0	0
T27	0	80368	0	0
T28	0	720	0	0
T29	0	111168	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804521594	649846144	0	0
T1	779629	496111	0	0
T2	1693128	1059253	0	0
T3	1190212	650827	0	0
T4	240933	216374	0	0
T5	1657845	994210	0	0
T6	1308	1219	0	0
T7	542008	340939	0	0
T8	1233691	793374	0	0
T9	5422	4356	0	0
T10	908	811	0	0
T11	937030	464592	0	0
T12	579384	289692	0	0
T13	0	120395	0	0
T14	0	127824	0	0
T24	0	98784	0	0
T25	0	114472	0	0
T27	0	80368	0	0
T28	0	720	0	0
T29	0	111168	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804521594	3851430	0	0
T1	779629	14051	0	0
T2	1693128	20433	0	0
T3	1190212	20684	0	0
T4	240933	832	0	0
T5	1657845	7816	0	0
T6	1308	0	0	0
T7	542008	5453	0	0
T8	1233691	13014	0	0
T9	5422	0	0	0
T10	908	0	0	0
T11	937030	9763	0	0
T12	579384	832	0	0
T13	0	12881	0	0
T15	0	9079	0	0
T23	0	832	0	0
T25	0	7180	0	0
T29	0	4542	0	0
T34	0	1171	0	0
T35	0	1032	0	0
T42	0	3095	0	0
T43	0	4224	0	0
T44	0	1543	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804521594	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804521594	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804521594	3851430	0	0
T1	779629	14051	0	0
T2	1693128	20433	0	0
T3	1190212	20684	0	0
T4	240933	832	0	0
T5	1657845	7816	0	0
T6	1308	0	0	0
T7	542008	5453	0	0
T8	1233691	13014	0	0
T9	5422	0	0	0
T10	908	0	0	0
T11	937030	9763	0	0
T12	579384	832	0	0
T13	0	12881	0	0
T15	0	9079	0	0
T23	0	832	0	0
T25	0	7180	0	0
T29	0	4542	0	0
T34	0	1171	0	0
T35	0	1032	0	0
T42	0	3095	0	0
T43	0	4224	0	0
T44	0	1543	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804521594	3851430	0	0
T1	779629	14051	0	0
T2	1693128	20433	0	0
T3	1190212	20684	0	0
T4	240933	832	0	0
T5	1657845	7816	0	0
T6	1308	0	0	0
T7	542008	5453	0	0
T8	1233691	13014	0	0
T9	5422	0	0	0
T10	908	0	0	0
T11	937030	9763	0	0
T12	579384	832	0	0
T13	0	12881	0	0
T15	0	9079	0	0
T23	0	832	0	0
T25	0	7180	0	0
T29	0	4542	0	0
T34	0	1171	0	0
T35	0	1032	0	0
T42	0	3095	0	0
T43	0	4224	0	0
T44	0	1543	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804521594	3851430	0	0
T1	779629	14051	0	0
T2	1693128	20433	0	0
T3	1190212	20684	0	0
T4	240933	832	0	0
T5	1657845	7816	0	0
T6	1308	0	0	0
T7	542008	5453	0	0
T8	1233691	13014	0	0
T9	5422	0	0	0
T10	908	0	0	0
T11	937030	9763	0	0
T12	579384	832	0	0
T13	0	12881	0	0
T15	0	9079	0	0
T23	0	832	0	0
T25	0	7180	0	0
T29	0	4542	0	0
T34	0	1171	0	0
T35	0	1032	0	0
T42	0	3095	0	0
T43	0	4224	0	0
T44	0	1543	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	804521594	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804521594	11	0	955
T45	180488	2	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	42866	0	0	1
T56	12990	0	0	1
T57	263566	0	0	1
T58	215678	0	0	1
T59	77084	0	0	1
T60	136368	0	0	1
T61	194713	0	0	1
T62	176293	0	0	1
T63	987	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804521594	649846144	0	0
T1	779629	496111	0	0
T2	1693128	1059253	0	0
T3	1190212	650827	0	0
T4	240933	216374	0	0
T5	1657845	994210	0	0
T6	1308	1219	0	0
T7	542008	340939	0	0
T8	1233691	793374	0	0
T9	5422	4356	0	0
T10	908	811	0	0
T11	937030	464592	0	0
T12	579384	289692	0	0
T13	0	120395	0	0
T14	0	127824	0	0
T24	0	98784	0	0
T25	0	114472	0	0
T27	0	80368	0	0
T28	0	720	0	0
T29	0	111168	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804521594	3851430	0	0
T1	779629	14051	0	0
T2	1693128	20433	0	0
T3	1190212	20684	0	0
T4	240933	832	0	0
T5	1657845	7816	0	0
T6	1308	0	0	0
T7	542008	5453	0	0
T8	1233691	13014	0	0
T9	5422	0	0	0
T10	908	0	0	0
T11	937030	9763	0	0
T12	579384	832	0	0
T13	0	12881	0	0
T15	0	9079	0	0
T23	0	832	0	0
T25	0	7180	0	0
T29	0	4542	0	0
T34	0	1171	0	0
T35	0	1032	0	0
T42	0	3095	0	0
T43	0	4224	0	0
T44	0	1543	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Unreachable
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153264979	27410895	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	153264979	605710	0	0
GntImpliesValid_A	153264979	605710	0	0
GrantKnown_A	153264979	27410895	0	0
IdxKnown_A	153264979	27410895	0	0
IndexIsCorrect_A	153264979	605710	0	0
LockArbDecision_A	153264979	0	0	0
NoReadyValidNoGrant_A	153264979	0	0	0
ReadyAndValidImplyGrant_A	153264979	605710	0	0
ReqAndReadyImplyGrant_A	153264979	605710	0	0
ReqImpliesValid_A	153264979	605710	0	0
ReqStaysHighUntilGranted0_M	153264979	0	0	0
RoundRobin_A	153264979	0	0	0
ValidKnown_A	153264979	27410895	0	0
gen_data_port_assertion.DataFlow_A	153264979	605710	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	27410895	0	0
T1	277646	117648	0	0
T2	624599	122544	0	0
T3	538172	0	0	0
T4	24031	0	0	0
T5	661516	0	0	0
T7	196206	191400	0	0
T8	438607	0	0	0
T9	851	720	0	0
T11	468515	214288	0	0
T12	289692	0	0	0
T24	0	98784	0	0
T25	0	114472	0	0
T27	0	80368	0	0
T28	0	720	0	0
T29	0	111168	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	605710	0	0
T1	277646	5473	0	0
T2	624599	6064	0	0
T3	538172	0	0	0
T4	24031	0	0	0
T5	661516	0	0	0
T7	196206	3834	0	0
T8	438607	0	0	0
T9	851	0	0	0
T11	468515	2854	0	0
T12	289692	0	0	0
T15	0	9079	0	0
T25	0	4863	0	0
T29	0	4542	0	0
T42	0	3095	0	0
T43	0	4224	0	0
T44	0	1543	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	605710	0	0
T1	277646	5473	0	0
T2	624599	6064	0	0
T3	538172	0	0	0
T4	24031	0	0	0
T5	661516	0	0	0
T7	196206	3834	0	0
T8	438607	0	0	0
T9	851	0	0	0
T11	468515	2854	0	0
T12	289692	0	0	0
T15	0	9079	0	0
T25	0	4863	0	0
T29	0	4542	0	0
T42	0	3095	0	0
T43	0	4224	0	0
T44	0	1543	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	27410895	0	0
T1	277646	117648	0	0
T2	624599	122544	0	0
T3	538172	0	0	0
T4	24031	0	0	0
T5	661516	0	0	0
T7	196206	191400	0	0
T8	438607	0	0	0
T9	851	720	0	0
T11	468515	214288	0	0
T12	289692	0	0	0
T24	0	98784	0	0
T25	0	114472	0	0
T27	0	80368	0	0
T28	0	720	0	0
T29	0	111168	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	27410895	0	0
T1	277646	117648	0	0
T2	624599	122544	0	0
T3	538172	0	0	0
T4	24031	0	0	0
T5	661516	0	0	0
T7	196206	191400	0	0
T8	438607	0	0	0
T9	851	720	0	0
T11	468515	214288	0	0
T12	289692	0	0	0
T24	0	98784	0	0
T25	0	114472	0	0
T27	0	80368	0	0
T28	0	720	0	0
T29	0	111168	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	605710	0	0
T1	277646	5473	0	0
T2	624599	6064	0	0
T3	538172	0	0	0
T4	24031	0	0	0
T5	661516	0	0	0
T7	196206	3834	0	0
T8	438607	0	0	0
T9	851	0	0	0
T11	468515	2854	0	0
T12	289692	0	0	0
T15	0	9079	0	0
T25	0	4863	0	0
T29	0	4542	0	0
T42	0	3095	0	0
T43	0	4224	0	0
T44	0	1543	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	605710	0	0
T1	277646	5473	0	0
T2	624599	6064	0	0
T3	538172	0	0	0
T4	24031	0	0	0
T5	661516	0	0	0
T7	196206	3834	0	0
T8	438607	0	0	0
T9	851	0	0	0
T11	468515	2854	0	0
T12	289692	0	0	0
T15	0	9079	0	0
T25	0	4863	0	0
T29	0	4542	0	0
T42	0	3095	0	0
T43	0	4224	0	0
T44	0	1543	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	605710	0	0
T1	277646	5473	0	0
T2	624599	6064	0	0
T3	538172	0	0	0
T4	24031	0	0	0
T5	661516	0	0	0
T7	196206	3834	0	0
T8	438607	0	0	0
T9	851	0	0	0
T11	468515	2854	0	0
T12	289692	0	0	0
T15	0	9079	0	0
T25	0	4863	0	0
T29	0	4542	0	0
T42	0	3095	0	0
T43	0	4224	0	0
T44	0	1543	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	605710	0	0
T1	277646	5473	0	0
T2	624599	6064	0	0
T3	538172	0	0	0
T4	24031	0	0	0
T5	661516	0	0	0
T7	196206	3834	0	0
T8	438607	0	0	0
T9	851	0	0	0
T11	468515	2854	0	0
T12	289692	0	0	0
T15	0	9079	0	0
T25	0	4863	0	0
T29	0	4542	0	0
T42	0	3095	0	0
T43	0	4224	0	0
T44	0	1543	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	27410895	0	0
T1	277646	117648	0	0
T2	624599	122544	0	0
T3	538172	0	0	0
T4	24031	0	0	0
T5	661516	0	0	0
T7	196206	191400	0	0
T8	438607	0	0	0
T9	851	720	0	0
T11	468515	214288	0	0
T12	289692	0	0	0
T24	0	98784	0	0
T25	0	114472	0	0
T27	0	80368	0	0
T28	0	720	0	0
T29	0	111168	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	605710	0	0
T1	277646	5473	0	0
T2	624599	6064	0	0
T3	538172	0	0	0
T4	24031	0	0	0
T5	661516	0	0	0
T7	196206	3834	0	0
T8	438607	0	0	0
T9	851	0	0	0
T11	468515	2854	0	0
T12	289692	0	0	0
T15	0	9079	0	0
T25	0	4863	0	0
T29	0	4542	0	0
T42	0	3095	0	0
T43	0	4224	0	0
T44	0	1543	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153264979	124529826	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	153264979	907635	0	0
GntImpliesValid_A	153264979	907635	0	0
GrantKnown_A	153264979	124529826	0	0
IdxKnown_A	153264979	124529826	0	0
IndexIsCorrect_A	153264979	907635	0	0
LockArbDecision_A	153264979	0	0	0
NoReadyValidNoGrant_A	153264979	0	0	0
ReadyAndValidImplyGrant_A	153264979	907635	0	0
ReqAndReadyImplyGrant_A	153264979	907635	0	0
ReqImpliesValid_A	153264979	907635	0	0
ReqStaysHighUntilGranted0_M	153264979	0	0	0
RoundRobin_A	153264979	0	0	0
ValidKnown_A	153264979	124529826	0	0
gen_data_port_assertion.DataFlow_A	153264979	907635	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	124529826	0	0
T1	277646	154132	0	0
T2	624599	492803	0	0
T3	538172	536966	0	0
T4	24031	23588	0	0
T5	661516	659406	0	0
T7	196206	0	0	0
T8	438607	436905	0	0
T9	851	0	0	0
T11	468515	250304	0	0
T12	289692	289692	0	0
T13	0	120395	0	0
T14	0	127824	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	907635	0	0
T1	277646	2454	0	0
T2	624599	1314	0	0
T3	538172	14230	0	0
T4	24031	0	0	0
T5	661516	260	0	0
T7	196206	0	0	0
T8	438607	6023	0	0
T9	851	0	0	0
T11	468515	2934	0	0
T12	289692	0	0	0
T13	0	12881	0	0
T25	0	2317	0	0
T34	0	1171	0	0
T35	0	1032	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	907635	0	0
T1	277646	2454	0	0
T2	624599	1314	0	0
T3	538172	14230	0	0
T4	24031	0	0	0
T5	661516	260	0	0
T7	196206	0	0	0
T8	438607	6023	0	0
T9	851	0	0	0
T11	468515	2934	0	0
T12	289692	0	0	0
T13	0	12881	0	0
T25	0	2317	0	0
T34	0	1171	0	0
T35	0	1032	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	124529826	0	0
T1	277646	154132	0	0
T2	624599	492803	0	0
T3	538172	536966	0	0
T4	24031	23588	0	0
T5	661516	659406	0	0
T7	196206	0	0	0
T8	438607	436905	0	0
T9	851	0	0	0
T11	468515	250304	0	0
T12	289692	289692	0	0
T13	0	120395	0	0
T14	0	127824	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	124529826	0	0
T1	277646	154132	0	0
T2	624599	492803	0	0
T3	538172	536966	0	0
T4	24031	23588	0	0
T5	661516	659406	0	0
T7	196206	0	0	0
T8	438607	436905	0	0
T9	851	0	0	0
T11	468515	250304	0	0
T12	289692	289692	0	0
T13	0	120395	0	0
T14	0	127824	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	907635	0	0
T1	277646	2454	0	0
T2	624599	1314	0	0
T3	538172	14230	0	0
T4	24031	0	0	0
T5	661516	260	0	0
T7	196206	0	0	0
T8	438607	6023	0	0
T9	851	0	0	0
T11	468515	2934	0	0
T12	289692	0	0	0
T13	0	12881	0	0
T25	0	2317	0	0
T34	0	1171	0	0
T35	0	1032	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	907635	0	0
T1	277646	2454	0	0
T2	624599	1314	0	0
T3	538172	14230	0	0
T4	24031	0	0	0
T5	661516	260	0	0
T7	196206	0	0	0
T8	438607	6023	0	0
T9	851	0	0	0
T11	468515	2934	0	0
T12	289692	0	0	0
T13	0	12881	0	0
T25	0	2317	0	0
T34	0	1171	0	0
T35	0	1032	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	907635	0	0
T1	277646	2454	0	0
T2	624599	1314	0	0
T3	538172	14230	0	0
T4	24031	0	0	0
T5	661516	260	0	0
T7	196206	0	0	0
T8	438607	6023	0	0
T9	851	0	0	0
T11	468515	2934	0	0
T12	289692	0	0	0
T13	0	12881	0	0
T25	0	2317	0	0
T34	0	1171	0	0
T35	0	1032	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	907635	0	0
T1	277646	2454	0	0
T2	624599	1314	0	0
T3	538172	14230	0	0
T4	24031	0	0	0
T5	661516	260	0	0
T7	196206	0	0	0
T8	438607	6023	0	0
T9	851	0	0	0
T11	468515	2934	0	0
T12	289692	0	0	0
T13	0	12881	0	0
T25	0	2317	0	0
T34	0	1171	0	0
T35	0	1032	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	124529826	0	0
T1	277646	154132	0	0
T2	624599	492803	0	0
T3	538172	536966	0	0
T4	24031	23588	0	0
T5	661516	659406	0	0
T7	196206	0	0	0
T8	438607	436905	0	0
T9	851	0	0	0
T11	468515	250304	0	0
T12	289692	289692	0	0
T13	0	120395	0	0
T14	0	127824	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264979	907635	0	0
T1	277646	2454	0	0
T2	624599	1314	0	0
T3	538172	14230	0	0
T4	24031	0	0	0
T5	661516	260	0	0
T7	196206	0	0	0
T8	438607	6023	0	0
T9	851	0	0	0
T11	468515	2934	0	0
T12	289692	0	0	0
T13	0	12881	0	0
T25	0	2317	0	0
T34	0	1171	0	0
T35	0	1032	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	497991636	497905423	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	497991636	2338085	0	0
GntImpliesValid_A	497991636	2338085	0	0
GrantKnown_A	497991636	497905423	0	0
IdxKnown_A	497991636	497905423	0	0
IndexIsCorrect_A	497991636	2338085	0	0
LockArbDecision_A	497991636	0	0	0
NoReadyValidNoGrant_A	497991636	0	0	0
ReadyAndValidImplyGrant_A	497991636	2338085	0	0
ReqAndReadyImplyGrant_A	497991636	2338085	0	0
ReqImpliesValid_A	497991636	2338085	0	0
ReqStaysHighUntilGranted0_M	497991636	0	0	0
RoundRobin_A	497991636	11	0	955
ValidKnown_A	497991636	497905423	0	0
gen_data_port_assertion.DataFlow_A	497991636	2338085	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	497905423	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	2338085	0	0
T1	224337	6124	0	0
T2	443930	13055	0	0
T3	113868	6454	0	0
T4	192871	832	0	0
T5	334813	7556	0	0
T6	1308	0	0	0
T7	149596	1619	0	0
T8	356477	6991	0	0
T9	3720	0	0	0
T10	908	0	0	0
T11	0	3975	0	0
T12	0	832	0	0
T23	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	2338085	0	0
T1	224337	6124	0	0
T2	443930	13055	0	0
T3	113868	6454	0	0
T4	192871	832	0	0
T5	334813	7556	0	0
T6	1308	0	0	0
T7	149596	1619	0	0
T8	356477	6991	0	0
T9	3720	0	0	0
T10	908	0	0	0
T11	0	3975	0	0
T12	0	832	0	0
T23	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	497905423	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	497905423	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	2338085	0	0
T1	224337	6124	0	0
T2	443930	13055	0	0
T3	113868	6454	0	0
T4	192871	832	0	0
T5	334813	7556	0	0
T6	1308	0	0	0
T7	149596	1619	0	0
T8	356477	6991	0	0
T9	3720	0	0	0
T10	908	0	0	0
T11	0	3975	0	0
T12	0	832	0	0
T23	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	2338085	0	0
T1	224337	6124	0	0
T2	443930	13055	0	0
T3	113868	6454	0	0
T4	192871	832	0	0
T5	334813	7556	0	0
T6	1308	0	0	0
T7	149596	1619	0	0
T8	356477	6991	0	0
T9	3720	0	0	0
T10	908	0	0	0
T11	0	3975	0	0
T12	0	832	0	0
T23	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	2338085	0	0
T1	224337	6124	0	0
T2	443930	13055	0	0
T3	113868	6454	0	0
T4	192871	832	0	0
T5	334813	7556	0	0
T6	1308	0	0	0
T7	149596	1619	0	0
T8	356477	6991	0	0
T9	3720	0	0	0
T10	908	0	0	0
T11	0	3975	0	0
T12	0	832	0	0
T23	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	2338085	0	0
T1	224337	6124	0	0
T2	443930	13055	0	0
T3	113868	6454	0	0
T4	192871	832	0	0
T5	334813	7556	0	0
T6	1308	0	0	0
T7	149596	1619	0	0
T8	356477	6991	0	0
T9	3720	0	0	0
T10	908	0	0	0
T11	0	3975	0	0
T12	0	832	0	0
T23	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	11	0	955
T45	180488	2	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	42866	0	0	1
T56	12990	0	0	1
T57	263566	0	0	1
T58	215678	0	0	1
T59	77084	0	0	1
T60	136368	0	0	1
T61	194713	0	0	1
T62	176293	0	0	1
T63	987	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	497905423	0	0
T1	224337	224331	0	0
T2	443930	443906	0	0
T3	113868	113861	0	0
T4	192871	192786	0	0
T5	334813	334804	0	0
T6	1308	1219	0	0
T7	149596	149539	0	0
T8	356477	356469	0	0
T9	3720	3636	0	0
T10	908	811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497991636	2338085	0	0
T1	224337	6124	0	0
T2	443930	13055	0	0
T3	113868	6454	0	0
T4	192871	832	0	0
T5	334813	7556	0	0
T6	1308	0	0	0
T7	149596	1619	0	0
T8	356477	6991	0	0
T9	3720	0	0	0
T10	908	0	0	0
T11	0	3975	0	0
T12	0	832	0	0
T23	0	832	0	0