Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3671662	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4198510

1

T1

1159

T2

6533

T3

1015

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4416086	1			T1	524		T2	776		T3	311
values[0x0]	1726488	1			T1	453		T2	3131		T3	426
values[0x1]	1727598	1			T1	433		T2	3022		T3	453

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2602775	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5267397

1

T1

1213

T2

6625

T3

1051

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31157	1			T2	17		T8	4		T9	66
valid_sources[0x01]	28574	1			T2	21		T9	40		T10	5
valid_sources[0x02]	31364	1			T2	28		T8	1		T9	41
valid_sources[0x03]	28174	1			T2	12		T8	2		T9	32
valid_sources[0x04]	33676	1			T2	40		T8	3		T9	51
valid_sources[0x05]	28196	1			T2	22		T8	2		T9	58
valid_sources[0x06]	28985	1			T2	29		T5	30		T8	2
valid_sources[0x07]	37151	1			T2	33		T5	27		T8	8
valid_sources[0x08]	31059	1			T2	28		T8	9		T9	49
valid_sources[0x09]	30418	1			T2	29		T5	111		T8	2
valid_sources[0x0a]	31315	1			T2	30		T8	2		T9	51
valid_sources[0x0b]	28865	1			T2	37		T8	3		T9	69
valid_sources[0x0c]	34772	1			T2	19		T8	6		T9	61
valid_sources[0x0d]	28439	1			T2	17		T8	3		T9	57
valid_sources[0x0e]	30266	1			T2	26		T9	54		T10	2
valid_sources[0x0f]	28159	1			T2	23		T8	1		T9	69
valid_sources[0x10]	30051	1			T2	37		T8	4		T9	72
valid_sources[0x11]	30023	1			T1	1410		T2	22		T8	2
valid_sources[0x12]	27201	1			T2	18		T8	7		T9	56
valid_sources[0x13]	27733	1			T2	33		T8	3		T9	63
valid_sources[0x14]	27835	1			T2	36		T8	10		T9	53
valid_sources[0x15]	34612	1			T2	22		T5	56		T8	7
valid_sources[0x16]	28191	1			T2	22		T8	1		T9	44
valid_sources[0x17]	27839	1			T2	29		T9	64		T10	4
valid_sources[0x18]	28623	1			T2	19		T8	1		T9	58
valid_sources[0x19]	28802	1			T2	37		T8	1		T9	55
valid_sources[0x1a]	36117	1			T2	23		T8	1		T9	52
valid_sources[0x1b]	31387	1			T2	28		T5	60		T8	2
valid_sources[0x1c]	28940	1			T2	16		T8	3		T9	63
valid_sources[0x1d]	30401	1			T2	48		T8	6		T9	54
valid_sources[0x1e]	31942	1			T2	30		T8	3		T9	41
valid_sources[0x1f]	31062	1			T2	22		T8	10		T9	52
valid_sources[0x20]	28949	1			T2	44		T8	10		T9	57
valid_sources[0x21]	34734	1			T2	15		T5	46		T6	1337
valid_sources[0x22]	29790	1			T2	36		T5	65		T9	48
valid_sources[0x23]	30629	1			T2	22		T8	10		T9	47
valid_sources[0x24]	27098	1			T2	33		T8	1		T9	51
valid_sources[0x25]	28968	1			T2	34		T8	10		T9	70
valid_sources[0x26]	28710	1			T2	17		T8	7		T9	55
valid_sources[0x27]	30492	1			T2	20		T8	3		T9	57
valid_sources[0x28]	29577	1			T2	25		T6	452		T8	7
valid_sources[0x29]	29337	1			T2	24		T8	9		T9	51
valid_sources[0x2a]	31124	1			T2	19		T8	7		T9	54
valid_sources[0x2b]	31439	1			T2	34		T5	5		T8	1
valid_sources[0x2c]	30737	1			T2	27		T5	72		T8	7
valid_sources[0x2d]	28212	1			T2	27		T8	5		T9	73
valid_sources[0x2e]	30072	1			T2	19		T5	9		T8	4
valid_sources[0x2f]	27594	1			T2	20		T8	5		T9	54
valid_sources[0x30]	28601	1			T2	30		T9	52		T10	5
valid_sources[0x31]	29112	1			T2	33		T8	2		T9	61
valid_sources[0x32]	30578	1			T2	23		T8	4		T9	66
valid_sources[0x33]	28063	1			T2	19		T5	10		T8	2
valid_sources[0x34]	30953	1			T2	26		T8	3		T9	63
valid_sources[0x35]	28229	1			T2	24		T7	134		T8	2
valid_sources[0x36]	33146	1			T2	40		T8	3		T9	63
valid_sources[0x37]	27725	1			T2	21		T8	3		T9	54
valid_sources[0x38]	28127	1			T2	31		T8	1		T9	57
valid_sources[0x39]	32055	1			T2	35		T8	2		T9	63
valid_sources[0x3a]	28280	1			T2	27		T8	3		T9	52
valid_sources[0x3b]	27522	1			T2	32		T8	2		T9	51
valid_sources[0x3c]	28708	1			T2	27		T8	5		T9	65
valid_sources[0x3d]	34834	1			T2	30		T8	4		T9	48
valid_sources[0x3e]	29097	1			T2	24		T5	76		T8	5
valid_sources[0x3f]	29723	1			T2	49		T5	41		T8	2
valid_sources[0x40]	28923	1			T2	18		T8	5		T9	69
valid_sources[0x41]	30780	1			T2	24		T8	2		T9	53
valid_sources[0x42]	28545	1			T2	25		T8	5		T9	55
valid_sources[0x43]	28645	1			T2	21		T5	24		T8	1
valid_sources[0x44]	30637	1			T2	36		T8	10		T9	53
valid_sources[0x45]	28922	1			T2	31		T9	60		T10	3
valid_sources[0x46]	31157	1			T2	31		T5	98		T8	7
valid_sources[0x47]	30160	1			T2	23		T5	57		T8	2
valid_sources[0x48]	29893	1			T2	37		T8	1		T9	61
valid_sources[0x49]	32280	1			T2	29		T8	8		T9	61
valid_sources[0x4a]	28893	1			T2	20		T8	3		T9	53
valid_sources[0x4b]	27874	1			T2	24		T8	2		T9	64
valid_sources[0x4c]	31223	1			T2	23		T8	1		T9	65
valid_sources[0x4d]	27469	1			T2	25		T5	21		T9	43
valid_sources[0x4e]	32159	1			T2	42		T8	2		T9	43
valid_sources[0x4f]	27895	1			T2	14		T8	5		T9	39
valid_sources[0x50]	27830	1			T2	31		T5	26		T8	1
valid_sources[0x51]	29011	1			T2	26		T8	4		T9	50
valid_sources[0x52]	28908	1			T2	38		T9	45		T10	5
valid_sources[0x53]	28734	1			T2	27		T5	117		T8	6
valid_sources[0x54]	29579	1			T2	39		T8	3		T9	56
valid_sources[0x55]	27791	1			T2	29		T5	10		T8	1
valid_sources[0x56]	28276	1			T2	21		T5	3		T8	2
valid_sources[0x57]	27742	1			T2	20		T8	6		T9	60
valid_sources[0x58]	28025	1			T2	28		T8	2		T9	54
valid_sources[0x59]	30136	1			T2	17		T8	3		T9	54
valid_sources[0x5a]	29470	1			T2	25		T8	3		T9	49
valid_sources[0x5b]	27389	1			T2	32		T8	5		T9	54
valid_sources[0x5c]	32009	1			T2	27		T5	5		T9	48
valid_sources[0x5d]	30567	1			T2	34		T8	2		T9	52
valid_sources[0x5e]	28426	1			T2	27		T8	5		T9	45
valid_sources[0x5f]	28713	1			T2	27		T8	1		T9	51
valid_sources[0x60]	32301	1			T2	34		T8	14		T9	62
valid_sources[0x61]	29942	1			T2	25		T9	57		T10	3
valid_sources[0x62]	30483	1			T2	29		T5	16		T8	2
valid_sources[0x63]	28825	1			T2	17		T9	64		T10	6
valid_sources[0x64]	30035	1			T2	37		T9	57		T10	2
valid_sources[0x65]	52131	1			T2	44		T8	4		T9	61
valid_sources[0x66]	28238	1			T2	26		T9	43		T10	1
valid_sources[0x67]	27628	1			T2	19		T9	40		T10	4
valid_sources[0x68]	31701	1			T2	34		T8	5		T9	58
valid_sources[0x69]	31801	1			T2	31		T8	1		T9	47
valid_sources[0x6a]	28981	1			T2	30		T8	6		T9	56
valid_sources[0x6b]	34586	1			T2	18		T8	3		T9	56
valid_sources[0x6c]	29003	1			T2	39		T9	46		T10	6
valid_sources[0x6d]	30819	1			T2	27		T5	39		T8	2
valid_sources[0x6e]	35349	1			T2	15		T8	5		T9	60
valid_sources[0x6f]	30436	1			T2	21		T5	21		T9	57
valid_sources[0x70]	29095	1			T2	23		T5	53		T8	19
valid_sources[0x71]	27113	1			T2	28		T9	63		T10	1
valid_sources[0x72]	31527	1			T2	34		T8	1		T9	58
valid_sources[0x73]	29174	1			T2	31		T8	4		T9	58
valid_sources[0x74]	27782	1			T2	23		T8	1		T9	52
valid_sources[0x75]	29375	1			T2	42		T9	50		T10	8
valid_sources[0x76]	39588	1			T2	19		T5	5		T8	3
valid_sources[0x77]	31580	1			T2	46		T8	1		T9	80
valid_sources[0x78]	35119	1			T2	21		T8	6		T9	53
valid_sources[0x79]	27188	1			T2	28		T9	55		T10	7
valid_sources[0x7a]	29461	1			T2	32		T8	7		T9	60
valid_sources[0x7b]	27698	1			T2	26		T8	2		T9	60
valid_sources[0x7c]	28595	1			T2	28		T5	158		T8	7
valid_sources[0x7d]	31930	1			T2	9		T8	1		T9	61
valid_sources[0x7e]	29213	1			T2	32		T5	2		T8	2
valid_sources[0x7f]	32233	1			T2	34		T8	9		T9	60
valid_sources[0x80]	30011	1			T2	21		T5	7		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1069376

1

T1

279

T2

413

T3

141

values[0x0]

all_enables

biggest_size

1575664

1

T1

452

T2

3122

T3

424

values[0x1]

all_enables

biggest_size

1553470

1

T1

428

T2

2998

T3

450