Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3694629

1

T1

251

T2

396

T3

175

full_word

4199817

1

T1

1159

T2

6533

T3

1015

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7894046	1			T1	1410		T2	6929		T3	1190
auto[TlIntgErrCmd]	156	1			T100	3		T101	4		T102	15
auto[TlIntgErrData]	114	1			T100	2		T101	3		T102	9
auto[TlIntgErrBoth]	130	1			T100	5		T101	3		T102	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4421030

1

T1

524

T2

776

T3

311

auto[1]

3473416

1

T1

886

T2

6153

T3

879

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3351144	1			T1	245		T2	363		T3	170
auto[TlIntgErrNone]	partial	auto[1]	343123	1			T1	6		T2	33		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	1069715	1			T1	279		T2	413		T3	141
auto[TlIntgErrNone]	full_word	auto[1]	3130064	1			T1	880		T2	6120		T3	874
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T100	1		T102	6		T171	1
auto[TlIntgErrCmd]	partial	auto[1]	87	1			T100	1		T101	2		T102	9
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T101	1		T172	1		T174	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T100	1		T101	1		T177	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T100	1		T101	1		T102	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T100	1		T101	2		T102	5
auto[TlIntgErrData]	full_word	auto[0]	6	1			T175	2		T174	1		T178	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T102	1		T179	1		T180	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T100	1		T101	1		T102	3
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T100	4		T101	2		T102	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T177	1		T173	1		T181	2
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T173	1		T174	1		T182	1