Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	593969284	3270389	0	0
gen_wmask[1].MaskCheckPortA_A	593969284	3270389	0	0
gen_wmask[2].MaskCheckPortA_A	593969284	3270389	0	0
gen_wmask[3].MaskCheckPortA_A	593969284	3270389	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593969284	3270389	0	0
T1	11858	832	0	0
T2	725082	8581	0	0
T3	62256	832	0	0
T4	1548	0	0	0
T5	82876	832	0	0
T6	196273	832	0	0
T7	4598	85	0	0
T8	6669	832	0	0
T9	667032	12509	0	0
T10	295781	832	0	0
T11	576	0	0	0
T12	8000	832	0	0
T14	0	25884	0	0
T24	0	264	0	0
T33	0	7561	0	0
T34	0	2392	0	0
T35	0	123	0	0
T36	0	6040	0	0
T37	0	5527	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593969284	3270389	0	0
T1	11858	832	0	0
T2	725082	8581	0	0
T3	62256	832	0	0
T4	1548	0	0	0
T5	82876	832	0	0
T6	196273	832	0	0
T7	4598	85	0	0
T8	6669	832	0	0
T9	667032	12509	0	0
T10	295781	832	0	0
T11	576	0	0	0
T12	8000	832	0	0
T14	0	25884	0	0
T24	0	264	0	0
T33	0	7561	0	0
T34	0	2392	0	0
T35	0	123	0	0
T36	0	6040	0	0
T37	0	5527	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593969284	3270389	0	0
T1	11858	832	0	0
T2	725082	8581	0	0
T3	62256	832	0	0
T4	1548	0	0	0
T5	82876	832	0	0
T6	196273	832	0	0
T7	4598	85	0	0
T8	6669	832	0	0
T9	667032	12509	0	0
T10	295781	832	0	0
T11	576	0	0	0
T12	8000	832	0	0
T14	0	25884	0	0
T24	0	264	0	0
T33	0	7561	0	0
T34	0	2392	0	0
T35	0	123	0	0
T36	0	6040	0	0
T37	0	5527	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593969284	3270389	0	0
T1	11858	832	0	0
T2	725082	8581	0	0
T3	62256	832	0	0
T4	1548	0	0	0
T5	82876	832	0	0
T6	196273	832	0	0
T7	4598	85	0	0
T8	6669	832	0	0
T9	667032	12509	0	0
T10	295781	832	0	0
T11	576	0	0	0
T12	8000	832	0	0
T14	0	25884	0	0
T24	0	264	0	0
T33	0	7561	0	0
T34	0	2392	0	0
T35	0	123	0	0
T36	0	6040	0	0
T37	0	5527	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	451501096	2015392	0	0
gen_wmask[1].MaskCheckPortA_A	451501096	2015392	0	0
gen_wmask[2].MaskCheckPortA_A	451501096	2015392	0	0
gen_wmask[3].MaskCheckPortA_A	451501096	2015392	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	2015392	0	0
T1	11858	832	0	0
T2	213499	5824	0	0
T3	23360	832	0	0
T4	1548	0	0	0
T5	72909	832	0	0
T6	172193	832	0	0
T7	3078	17	0	0
T8	6511	832	0	0
T9	298607	9152	0	0
T10	200133	832	0	0
T12	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	2015392	0	0
T1	11858	832	0	0
T2	213499	5824	0	0
T3	23360	832	0	0
T4	1548	0	0	0
T5	72909	832	0	0
T6	172193	832	0	0
T7	3078	17	0	0
T8	6511	832	0	0
T9	298607	9152	0	0
T10	200133	832	0	0
T12	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	2015392	0	0
T1	11858	832	0	0
T2	213499	5824	0	0
T3	23360	832	0	0
T4	1548	0	0	0
T5	72909	832	0	0
T6	172193	832	0	0
T7	3078	17	0	0
T8	6511	832	0	0
T9	298607	9152	0	0
T10	200133	832	0	0
T12	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	2015392	0	0
T1	11858	832	0	0
T2	213499	5824	0	0
T3	23360	832	0	0
T4	1548	0	0	0
T5	72909	832	0	0
T6	172193	832	0	0
T7	3078	17	0	0
T8	6511	832	0	0
T9	298607	9152	0	0
T10	200133	832	0	0
T12	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	142468188	1254997	0	0
gen_wmask[1].MaskCheckPortA_A	142468188	1254997	0	0
gen_wmask[2].MaskCheckPortA_A	142468188	1254997	0	0
gen_wmask[3].MaskCheckPortA_A	142468188	1254997	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	1254997	0	0
T2	511583	2757	0	0
T3	38896	0	0	0
T5	9967	0	0	0
T6	24080	0	0	0
T7	1520	68	0	0
T8	158	0	0	0
T9	368425	3357	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T14	0	25884	0	0
T24	0	264	0	0
T33	0	7561	0	0
T34	0	2392	0	0
T35	0	123	0	0
T36	0	6040	0	0
T37	0	5527	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	1254997	0	0
T2	511583	2757	0	0
T3	38896	0	0	0
T5	9967	0	0	0
T6	24080	0	0	0
T7	1520	68	0	0
T8	158	0	0	0
T9	368425	3357	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T14	0	25884	0	0
T24	0	264	0	0
T33	0	7561	0	0
T34	0	2392	0	0
T35	0	123	0	0
T36	0	6040	0	0
T37	0	5527	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	1254997	0	0
T2	511583	2757	0	0
T3	38896	0	0	0
T5	9967	0	0	0
T6	24080	0	0	0
T7	1520	68	0	0
T8	158	0	0	0
T9	368425	3357	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T14	0	25884	0	0
T24	0	264	0	0
T33	0	7561	0	0
T34	0	2392	0	0
T35	0	123	0	0
T36	0	6040	0	0
T37	0	5527	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	1254997	0	0
T2	511583	2757	0	0
T3	38896	0	0	0
T5	9967	0	0	0
T6	24080	0	0	0
T7	1520	68	0	0
T8	158	0	0	0
T9	368425	3357	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T14	0	25884	0	0
T24	0	264	0	0
T33	0	7561	0	0
T34	0	2392	0	0
T35	0	123	0	0
T36	0	6040	0	0
T37	0	5527	0	0