Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T9
1	0	Covered	T2,T5,T9
1	1	Covered	T2,T5,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T9
1	0	Covered	T2,T5,T9
1	1	Covered	T2,T5,T9

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1354503288	2792	0	0
SrcPulseCheck_M	427404564	2792	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1354503288	2792	0	0
T2	213499	5	0	0
T3	23360	0	0	0
T4	1548	0	0	0
T5	218727	7	0	0
T6	516579	0	0	0
T7	9234	0	0	0
T8	19533	0	0	0
T9	895821	16	0	0
T10	600399	0	0	0
T11	11277	0	0	0
T12	14560	0	0	0
T13	294200	0	0	0
T14	0	53	0	0
T24	0	3	0	0
T25	0	12	0	0
T27	0	8	0	0
T30	137252	0	0	0
T33	0	13	0	0
T34	0	12	0	0
T36	0	22	0	0
T37	0	7	0	0
T43	0	4	0	0
T44	0	7	0	0
T45	0	7	0	0
T145	0	9	0	0
T146	0	7	0	0
T147	0	4	0	0
T148	0	7	0	0
T149	0	1	0	0
T150	0	5	0	0
T151	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427404564	2792	0	0
T2	511583	5	0	0
T3	38896	0	0	0
T5	29901	7	0	0
T6	72240	0	0	0
T7	4560	0	0	0
T8	474	0	0	0
T9	1105275	16	0	0
T10	286944	0	0	0
T11	1728	0	0	0
T12	24000	0	0	0
T13	95978	0	0	0
T14	0	53	0	0
T24	0	3	0	0
T25	0	12	0	0
T27	0	8	0	0
T30	281244	0	0	0
T33	0	13	0	0
T34	0	12	0	0
T36	0	22	0	0
T37	0	7	0	0
T43	0	4	0	0
T44	0	7	0	0
T45	0	7	0	0
T145	0	9	0	0
T146	0	7	0	0
T147	0	4	0	0
T148	0	7	0	0
T149	0	1	0	0
T150	0	5	0	0
T151	0	5	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T43,T44
1	0	Covered	T5,T43,T44
1	1	Covered	T5,T43,T44

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T43,T44
1	0	Covered	T5,T43,T44
1	1	Covered	T5,T43,T44

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	451501096	193	0	0
SrcPulseCheck_M	142468188	193	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	193	0	0
T5	72909	2	0	0
T6	172193	0	0	0
T7	3078	0	0	0
T8	6511	0	0	0
T9	298607	0	0	0
T10	200133	0	0	0
T11	3759	0	0	0
T12	7280	0	0	0
T13	147100	0	0	0
T30	68626	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T145	0	5	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	2	0	0
T149	0	1	0	0
T150	0	3	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	193	0	0
T5	9967	2	0	0
T6	24080	0	0	0
T7	1520	0	0	0
T8	158	0	0	0
T9	368425	0	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T13	47989	0	0	0
T30	140622	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T145	0	5	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	2	0	0
T149	0	1	0	0
T150	0	3	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T43,T44
1	0	Covered	T5,T43,T44
1	1	Covered	T5,T43,T44

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T43,T44
1	0	Covered	T5,T43,T44
1	1	Covered	T5,T43,T44

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	451501096	339	0	0
SrcPulseCheck_M	142468188	339	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	339	0	0
T5	72909	5	0	0
T6	172193	0	0	0
T7	3078	0	0	0
T8	6511	0	0	0
T9	298607	0	0	0
T10	200133	0	0	0
T11	3759	0	0	0
T12	7280	0	0	0
T13	147100	0	0	0
T30	68626	0	0	0
T43	0	2	0	0
T44	0	5	0	0
T45	0	5	0	0
T145	0	4	0	0
T146	0	5	0	0
T147	0	2	0	0
T148	0	5	0	0
T150	0	2	0	0
T151	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	339	0	0
T5	9967	5	0	0
T6	24080	0	0	0
T7	1520	0	0	0
T8	158	0	0	0
T9	368425	0	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T13	47989	0	0	0
T30	140622	0	0	0
T43	0	2	0	0
T44	0	5	0	0
T45	0	5	0	0
T145	0	4	0	0
T146	0	5	0	0
T147	0	2	0	0
T148	0	5	0	0
T150	0	2	0	0
T151	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T33
1	0	Covered	T2,T9,T33
1	1	Covered	T2,T9,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T33
1	0	Covered	T2,T9,T33
1	1	Covered	T2,T9,T33

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	451501096	2260	0	0
SrcPulseCheck_M	142468188	2260	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	2260	0	0
T2	213499	5	0	0
T3	23360	0	0	0
T4	1548	0	0	0
T5	72909	0	0	0
T6	172193	0	0	0
T7	3078	0	0	0
T8	6511	0	0	0
T9	298607	16	0	0
T10	200133	0	0	0
T11	3759	0	0	0
T14	0	53	0	0
T24	0	3	0	0
T25	0	12	0	0
T27	0	8	0	0
T33	0	13	0	0
T34	0	12	0	0
T36	0	22	0	0
T37	0	7	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	2260	0	0
T2	511583	5	0	0
T3	38896	0	0	0
T5	9967	0	0	0
T6	24080	0	0	0
T7	1520	0	0	0
T8	158	0	0	0
T9	368425	16	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T14	0	53	0	0
T24	0	3	0	0
T25	0	12	0	0
T27	0	8	0	0
T33	0	13	0	0
T34	0	12	0	0
T36	0	22	0	0
T37	0	7	0	0