Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	453681869	2805359	0	0
DepthKnown_A	453681869	453551771	0	0
RvalidKnown_A	453681869	453551771	0	0
WreadyKnown_A	453681869	453551771	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	2805359	0	0
T1	11858	832	0	0
T2	213499	9148	0	0
T3	23360	832	0	0
T4	1548	0	0	0
T5	72909	832	0	0
T6	172193	1671	0	0
T7	3078	0	0	0
T8	6511	832	0	0
T9	298607	14969	0	0
T10	200133	1669	0	0
T12	0	832	0	0
T13	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	453681869	3011523	0	0
DepthKnown_A	453681869	453551771	0	0
RvalidKnown_A	453681869	453551771	0	0
WreadyKnown_A	453681869	453551771	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	3011523	0	0
T1	11858	832	0	0
T2	213499	5824	0	0
T3	23360	3812	0	0
T4	1548	0	0	0
T5	72909	832	0	0
T6	172193	841	0	0
T7	3078	0	0	0
T8	6511	832	0	0
T9	298607	9152	0	0
T10	200133	839	0	0
T12	0	832	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	453681869	181862	0	0
DepthKnown_A	453681869	453551771	0	0
RvalidKnown_A	453681869	453551771	0	0
WreadyKnown_A	453681869	453551771	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	181862	0	0
T2	213499	65	0	0
T3	23360	0	0	0
T4	1548	0	0	0
T5	72909	0	0	0
T6	172193	0	0	0
T7	3078	17	0	0
T8	6511	0	0	0
T9	298607	448	0	0
T10	200133	0	0	0
T11	3759	0	0	0
T14	0	3398	0	0
T24	0	65	0	0
T33	0	630	0	0
T34	0	597	0	0
T35	0	32	0	0
T36	0	750	0	0
T37	0	1366	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	453681869	424154	0	0
DepthKnown_A	453681869	453551771	0	0
RvalidKnown_A	453681869	453551771	0	0
WreadyKnown_A	453681869	453551771	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	424154	0	0
T2	213499	65	0	0
T3	23360	0	0	0
T4	1548	0	0	0
T5	72909	0	0	0
T6	172193	0	0	0
T7	3078	72	0	0
T8	6511	0	0	0
T9	298607	448	0	0
T10	200133	0	0	0
T11	3759	0	0	0
T14	0	15370	0	0
T24	0	176	0	0
T33	0	3039	0	0
T34	0	1882	0	0
T35	0	151	0	0
T36	0	2253	0	0
T37	0	4047	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	453681869	6336503	0	0
DepthKnown_A	453681869	453551771	0	0
RvalidKnown_A	453681869	453551771	0	0
WreadyKnown_A	453681869	453551771	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	6336503	0	0
T1	11858	578	0	0
T2	213499	1042	0	0
T3	23360	358	0	0
T4	1548	1	0	0
T5	72909	1338	0	0
T6	172193	5308	0	0
T7	3078	117	0	0
T8	6511	54	0	0
T9	298607	4526	0	0
T10	200133	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	453681869	14000774	0	0
DepthKnown_A	453681869	453551771	0	0
RvalidKnown_A	453681869	453551771	0	0
WreadyKnown_A	453681869	453551771	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	14000774	0	0
T1	11858	578	0	0
T2	213499	1040	0	0
T3	23360	1524	0	0
T4	1548	1	0	0
T5	72909	1338	0	0
T6	172193	23273	0	0
T7	3078	502	0	0
T8	6511	54	0	0
T9	298607	4522	0	0
T10	200133	344	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453681869	453551771	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0