Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T33,T34
1	0	Covered	T7,T33,T34

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T30
1	0	Unreachable
1	1	Covered	T7,T33,T34

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T33

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T33
1	0	Covered	T2,T9,T33

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T9,T33

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	736437472	592596767	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	736437472	3640504	0	0
GntImpliesValid_A	736437472	3640504	0	0
GrantKnown_A	736437472	592596767	0	0
IdxKnown_A	736437472	592596767	0	0
IndexIsCorrect_A	736437472	3640504	0	0
LockArbDecision_A	736437472	0	0	0
NoReadyValidNoGrant_A	736437472	0	0	0
ReadyAndValidImplyGrant_A	736437472	3640504	0	0
ReqAndReadyImplyGrant_A	736437472	3640504	0	0
ReqImpliesValid_A	736437472	3640504	0	0
ReqStaysHighUntilGranted0_M	736437472	0	0	0
RoundRobin_A	736437472	4	0	956
ValidKnown_A	736437472	592596767	0	0
gen_data_port_assertion.DataFlow_A	736437472	3640504	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736437472	592596767	0	0
T1	38596	38531	0	0
T2	725082	723906	0	0
T3	62256	62169	0	0
T4	1548	1464	0	0
T5	82876	82780	0	0
T6	196273	196200	0	0
T7	6118	4501	0	0
T8	6827	6604	0	0
T9	1035457	665266	0	0
T10	391429	295077	0	0
T11	1152	576	0	0
T12	8000	8000	0	0
T13	47989	47744	0	0
T30	140622	134856	0	0
T31	90726	87592	0	0
T32	792	792	0	0
T33	0	43368	0	0
T34	0	44304	0	0
T35	0	2344	0	0
T36	0	13792	0	0
T37	0	565968	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736437472	3640504	0	0
T1	11858	832	0	0
T2	725082	8655	0	0
T3	62256	832	0	0
T4	1548	0	0	0
T5	82876	832	0	0
T6	196273	832	0	0
T7	6118	120	0	0
T8	6827	832	0	0
T9	1035457	12984	0	0
T10	391429	832	0	0
T11	1152	0	0	0
T12	16000	832	0	0
T13	47989	0	0	0
T14	0	29816	0	0
T24	0	264	0	0
T25	0	20509	0	0
T27	0	269	0	0
T30	140622	0	0	0
T31	90726	0	0	0
T32	792	0	0	0
T33	0	8076	0	0
T34	0	2954	0	0
T35	0	134	0	0
T36	0	6257	0	0
T37	0	7584	0	0
T40	0	809	0	0
T53	0	228	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736437472	3640504	0	0
T1	11858	832	0	0
T2	725082	8655	0	0
T3	62256	832	0	0
T4	1548	0	0	0
T5	82876	832	0	0
T6	196273	832	0	0
T7	6118	120	0	0
T8	6827	832	0	0
T9	1035457	12984	0	0
T10	391429	832	0	0
T11	1152	0	0	0
T12	16000	832	0	0
T13	47989	0	0	0
T14	0	29816	0	0
T24	0	264	0	0
T25	0	20509	0	0
T27	0	269	0	0
T30	140622	0	0	0
T31	90726	0	0	0
T32	792	0	0	0
T33	0	8076	0	0
T34	0	2954	0	0
T35	0	134	0	0
T36	0	6257	0	0
T37	0	7584	0	0
T40	0	809	0	0
T53	0	228	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736437472	592596767	0	0
T1	38596	38531	0	0
T2	725082	723906	0	0
T3	62256	62169	0	0
T4	1548	1464	0	0
T5	82876	82780	0	0
T6	196273	196200	0	0
T7	6118	4501	0	0
T8	6827	6604	0	0
T9	1035457	665266	0	0
T10	391429	295077	0	0
T11	1152	576	0	0
T12	8000	8000	0	0
T13	47989	47744	0	0
T30	140622	134856	0	0
T31	90726	87592	0	0
T32	792	792	0	0
T33	0	43368	0	0
T34	0	44304	0	0
T35	0	2344	0	0
T36	0	13792	0	0
T37	0	565968	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736437472	592596767	0	0
T1	38596	38531	0	0
T2	725082	723906	0	0
T3	62256	62169	0	0
T4	1548	1464	0	0
T5	82876	82780	0	0
T6	196273	196200	0	0
T7	6118	4501	0	0
T8	6827	6604	0	0
T9	1035457	665266	0	0
T10	391429	295077	0	0
T11	1152	576	0	0
T12	8000	8000	0	0
T13	47989	47744	0	0
T30	140622	134856	0	0
T31	90726	87592	0	0
T32	792	792	0	0
T33	0	43368	0	0
T34	0	44304	0	0
T35	0	2344	0	0
T36	0	13792	0	0
T37	0	565968	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736437472	3640504	0	0
T1	11858	832	0	0
T2	725082	8655	0	0
T3	62256	832	0	0
T4	1548	0	0	0
T5	82876	832	0	0
T6	196273	832	0	0
T7	6118	120	0	0
T8	6827	832	0	0
T9	1035457	12984	0	0
T10	391429	832	0	0
T11	1152	0	0	0
T12	16000	832	0	0
T13	47989	0	0	0
T14	0	29816	0	0
T24	0	264	0	0
T25	0	20509	0	0
T27	0	269	0	0
T30	140622	0	0	0
T31	90726	0	0	0
T32	792	0	0	0
T33	0	8076	0	0
T34	0	2954	0	0
T35	0	134	0	0
T36	0	6257	0	0
T37	0	7584	0	0
T40	0	809	0	0
T53	0	228	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736437472	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736437472	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736437472	3640504	0	0
T1	11858	832	0	0
T2	725082	8655	0	0
T3	62256	832	0	0
T4	1548	0	0	0
T5	82876	832	0	0
T6	196273	832	0	0
T7	6118	120	0	0
T8	6827	832	0	0
T9	1035457	12984	0	0
T10	391429	832	0	0
T11	1152	0	0	0
T12	16000	832	0	0
T13	47989	0	0	0
T14	0	29816	0	0
T24	0	264	0	0
T25	0	20509	0	0
T27	0	269	0	0
T30	140622	0	0	0
T31	90726	0	0	0
T32	792	0	0	0
T33	0	8076	0	0
T34	0	2954	0	0
T35	0	134	0	0
T36	0	6257	0	0
T37	0	7584	0	0
T40	0	809	0	0
T53	0	228	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736437472	3640504	0	0
T1	11858	832	0	0
T2	725082	8655	0	0
T3	62256	832	0	0
T4	1548	0	0	0
T5	82876	832	0	0
T6	196273	832	0	0
T7	6118	120	0	0
T8	6827	832	0	0
T9	1035457	12984	0	0
T10	391429	832	0	0
T11	1152	0	0	0
T12	16000	832	0	0
T13	47989	0	0	0
T14	0	29816	0	0
T24	0	264	0	0
T25	0	20509	0	0
T27	0	269	0	0
T30	140622	0	0	0
T31	90726	0	0	0
T32	792	0	0	0
T33	0	8076	0	0
T34	0	2954	0	0
T35	0	134	0	0
T36	0	6257	0	0
T37	0	7584	0	0
T40	0	809	0	0
T53	0	228	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736437472	3640504	0	0
T1	11858	832	0	0
T2	725082	8655	0	0
T3	62256	832	0	0
T4	1548	0	0	0
T5	82876	832	0	0
T6	196273	832	0	0
T7	6118	120	0	0
T8	6827	832	0	0
T9	1035457	12984	0	0
T10	391429	832	0	0
T11	1152	0	0	0
T12	16000	832	0	0
T13	47989	0	0	0
T14	0	29816	0	0
T24	0	264	0	0
T25	0	20509	0	0
T27	0	269	0	0
T30	140622	0	0	0
T31	90726	0	0	0
T32	792	0	0	0
T33	0	8076	0	0
T34	0	2954	0	0
T35	0	134	0	0
T36	0	6257	0	0
T37	0	7584	0	0
T40	0	809	0	0
T53	0	228	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	736437472	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736437472	4	0	956
T54	558612	1	0	1
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	1405	0	0	1
T59	158681	0	0	1
T60	28825	0	0	1
T61	472722	0	0	1
T62	4572	0	0	1
T63	252295	0	0	1
T64	794396	0	0	1
T65	379400	0	0	1
T66	1624	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736437472	592596767	0	0
T1	38596	38531	0	0
T2	725082	723906	0	0
T3	62256	62169	0	0
T4	1548	1464	0	0
T5	82876	82780	0	0
T6	196273	196200	0	0
T7	6118	4501	0	0
T8	6827	6604	0	0
T9	1035457	665266	0	0
T10	391429	295077	0	0
T11	1152	576	0	0
T12	8000	8000	0	0
T13	47989	47744	0	0
T30	140622	134856	0	0
T31	90726	87592	0	0
T32	792	792	0	0
T33	0	43368	0	0
T34	0	44304	0	0
T35	0	2344	0	0
T36	0	13792	0	0
T37	0	565968	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736437472	3640504	0	0
T1	11858	832	0	0
T2	725082	8655	0	0
T3	62256	832	0	0
T4	1548	0	0	0
T5	82876	832	0	0
T6	196273	832	0	0
T7	6118	120	0	0
T8	6827	832	0	0
T9	1035457	12984	0	0
T10	391429	832	0	0
T11	1152	0	0	0
T12	16000	832	0	0
T13	47989	0	0	0
T14	0	29816	0	0
T24	0	264	0	0
T25	0	20509	0	0
T27	0	269	0	0
T30	140622	0	0	0
T31	90726	0	0	0
T32	792	0	0	0
T33	0	8076	0	0
T34	0	2954	0	0
T35	0	134	0	0
T36	0	6257	0	0
T37	0	7584	0	0
T40	0	809	0	0
T53	0	228	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T33,T34
1	0	Covered	T7,T33,T34

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T30
1	0	Unreachable
1	1	Covered	T7,T33,T34

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T33,T34
0	0	1	Unreachable
0	0	0	Covered	T7,T11,T30

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T33,T34
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T33,T34
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	142468188	25147800	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	142468188	597218	0	0
GntImpliesValid_A	142468188	597218	0	0
GrantKnown_A	142468188	25147800	0	0
IdxKnown_A	142468188	25147800	0	0
IndexIsCorrect_A	142468188	597218	0	0
LockArbDecision_A	142468188	0	0	0
NoReadyValidNoGrant_A	142468188	0	0	0
ReadyAndValidImplyGrant_A	142468188	597218	0	0
ReqAndReadyImplyGrant_A	142468188	597218	0	0
ReqImpliesValid_A	142468188	597218	0	0
ReqStaysHighUntilGranted0_M	142468188	0	0	0
RoundRobin_A	142468188	0	0	0
ValidKnown_A	142468188	25147800	0	0
gen_data_port_assertion.DataFlow_A	142468188	597218	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	25147800	0	0
T7	1520	1520	0	0
T8	158	0	0	0
T9	368425	0	0	0
T10	95648	0	0	0
T11	576	576	0	0
T12	8000	0	0	0
T13	47989	0	0	0
T30	140622	134856	0	0
T31	90726	87592	0	0
T32	792	792	0	0
T33	0	43368	0	0
T34	0	44304	0	0
T35	0	2344	0	0
T36	0	13792	0	0
T37	0	565968	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	597218	0	0
T7	1520	86	0	0
T8	158	0	0	0
T9	368425	0	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T13	47989	0	0	0
T14	0	11679	0	0
T25	0	1291	0	0
T30	140622	0	0	0
T31	90726	0	0	0
T32	792	0	0	0
T33	0	1460	0	0
T34	0	1772	0	0
T35	0	134	0	0
T36	0	668	0	0
T37	0	6033	0	0
T40	0	809	0	0
T53	0	228	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	597218	0	0
T7	1520	86	0	0
T8	158	0	0	0
T9	368425	0	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T13	47989	0	0	0
T14	0	11679	0	0
T25	0	1291	0	0
T30	140622	0	0	0
T31	90726	0	0	0
T32	792	0	0	0
T33	0	1460	0	0
T34	0	1772	0	0
T35	0	134	0	0
T36	0	668	0	0
T37	0	6033	0	0
T40	0	809	0	0
T53	0	228	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	25147800	0	0
T7	1520	1520	0	0
T8	158	0	0	0
T9	368425	0	0	0
T10	95648	0	0	0
T11	576	576	0	0
T12	8000	0	0	0
T13	47989	0	0	0
T30	140622	134856	0	0
T31	90726	87592	0	0
T32	792	792	0	0
T33	0	43368	0	0
T34	0	44304	0	0
T35	0	2344	0	0
T36	0	13792	0	0
T37	0	565968	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	25147800	0	0
T7	1520	1520	0	0
T8	158	0	0	0
T9	368425	0	0	0
T10	95648	0	0	0
T11	576	576	0	0
T12	8000	0	0	0
T13	47989	0	0	0
T30	140622	134856	0	0
T31	90726	87592	0	0
T32	792	792	0	0
T33	0	43368	0	0
T34	0	44304	0	0
T35	0	2344	0	0
T36	0	13792	0	0
T37	0	565968	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	597218	0	0
T7	1520	86	0	0
T8	158	0	0	0
T9	368425	0	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T13	47989	0	0	0
T14	0	11679	0	0
T25	0	1291	0	0
T30	140622	0	0	0
T31	90726	0	0	0
T32	792	0	0	0
T33	0	1460	0	0
T34	0	1772	0	0
T35	0	134	0	0
T36	0	668	0	0
T37	0	6033	0	0
T40	0	809	0	0
T53	0	228	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	597218	0	0
T7	1520	86	0	0
T8	158	0	0	0
T9	368425	0	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T13	47989	0	0	0
T14	0	11679	0	0
T25	0	1291	0	0
T30	140622	0	0	0
T31	90726	0	0	0
T32	792	0	0	0
T33	0	1460	0	0
T34	0	1772	0	0
T35	0	134	0	0
T36	0	668	0	0
T37	0	6033	0	0
T40	0	809	0	0
T53	0	228	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	597218	0	0
T7	1520	86	0	0
T8	158	0	0	0
T9	368425	0	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T13	47989	0	0	0
T14	0	11679	0	0
T25	0	1291	0	0
T30	140622	0	0	0
T31	90726	0	0	0
T32	792	0	0	0
T33	0	1460	0	0
T34	0	1772	0	0
T35	0	134	0	0
T36	0	668	0	0
T37	0	6033	0	0
T40	0	809	0	0
T53	0	228	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	597218	0	0
T7	1520	86	0	0
T8	158	0	0	0
T9	368425	0	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T13	47989	0	0	0
T14	0	11679	0	0
T25	0	1291	0	0
T30	140622	0	0	0
T31	90726	0	0	0
T32	792	0	0	0
T33	0	1460	0	0
T34	0	1772	0	0
T35	0	134	0	0
T36	0	668	0	0
T37	0	6033	0	0
T40	0	809	0	0
T53	0	228	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	25147800	0	0
T7	1520	1520	0	0
T8	158	0	0	0
T9	368425	0	0	0
T10	95648	0	0	0
T11	576	576	0	0
T12	8000	0	0	0
T13	47989	0	0	0
T30	140622	134856	0	0
T31	90726	87592	0	0
T32	792	792	0	0
T33	0	43368	0	0
T34	0	44304	0	0
T35	0	2344	0	0
T36	0	13792	0	0
T37	0	565968	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	597218	0	0
T7	1520	86	0	0
T8	158	0	0	0
T9	368425	0	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T13	47989	0	0	0
T14	0	11679	0	0
T25	0	1291	0	0
T30	140622	0	0	0
T31	90726	0	0	0
T32	792	0	0	0
T33	0	1460	0	0
T34	0	1772	0	0
T35	0	134	0	0
T36	0	668	0	0
T37	0	6033	0	0
T40	0	809	0	0
T53	0	228	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T33

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T33
1	0	Covered	T2,T9,T33

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T9,T33

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T33
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T9,T33
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T33
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T33
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	142468188	116032670	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	142468188	856287	0	0
GntImpliesValid_A	142468188	856287	0	0
GrantKnown_A	142468188	116032670	0	0
IdxKnown_A	142468188	116032670	0	0
IndexIsCorrect_A	142468188	856287	0	0
LockArbDecision_A	142468188	0	0	0
NoReadyValidNoGrant_A	142468188	0	0	0
ReadyAndValidImplyGrant_A	142468188	856287	0	0
ReqAndReadyImplyGrant_A	142468188	856287	0	0
ReqImpliesValid_A	142468188	856287	0	0
ReqStaysHighUntilGranted0_M	142468188	0	0	0
RoundRobin_A	142468188	0	0	0
ValidKnown_A	142468188	116032670	0	0
gen_data_port_assertion.DataFlow_A	142468188	856287	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	116032670	0	0
T1	26738	26738	0	0
T2	511583	510473	0	0
T3	38896	38896	0	0
T5	9967	9967	0	0
T6	24080	24080	0	0
T7	1520	0	0	0
T8	158	158	0	0
T9	368425	366669	0	0
T10	95648	95028	0	0
T11	576	0	0	0
T12	0	8000	0	0
T13	0	47744	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	856287	0	0
T2	511583	2757	0	0
T3	38896	0	0	0
T5	9967	0	0	0
T6	24080	0	0	0
T7	1520	0	0	0
T8	158	0	0	0
T9	368425	3357	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T14	0	18137	0	0
T24	0	264	0	0
T25	0	19218	0	0
T27	0	269	0	0
T33	0	6616	0	0
T34	0	1182	0	0
T36	0	5589	0	0
T37	0	1551	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	856287	0	0
T2	511583	2757	0	0
T3	38896	0	0	0
T5	9967	0	0	0
T6	24080	0	0	0
T7	1520	0	0	0
T8	158	0	0	0
T9	368425	3357	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T14	0	18137	0	0
T24	0	264	0	0
T25	0	19218	0	0
T27	0	269	0	0
T33	0	6616	0	0
T34	0	1182	0	0
T36	0	5589	0	0
T37	0	1551	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	116032670	0	0
T1	26738	26738	0	0
T2	511583	510473	0	0
T3	38896	38896	0	0
T5	9967	9967	0	0
T6	24080	24080	0	0
T7	1520	0	0	0
T8	158	158	0	0
T9	368425	366669	0	0
T10	95648	95028	0	0
T11	576	0	0	0
T12	0	8000	0	0
T13	0	47744	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	116032670	0	0
T1	26738	26738	0	0
T2	511583	510473	0	0
T3	38896	38896	0	0
T5	9967	9967	0	0
T6	24080	24080	0	0
T7	1520	0	0	0
T8	158	158	0	0
T9	368425	366669	0	0
T10	95648	95028	0	0
T11	576	0	0	0
T12	0	8000	0	0
T13	0	47744	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	856287	0	0
T2	511583	2757	0	0
T3	38896	0	0	0
T5	9967	0	0	0
T6	24080	0	0	0
T7	1520	0	0	0
T8	158	0	0	0
T9	368425	3357	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T14	0	18137	0	0
T24	0	264	0	0
T25	0	19218	0	0
T27	0	269	0	0
T33	0	6616	0	0
T34	0	1182	0	0
T36	0	5589	0	0
T37	0	1551	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	856287	0	0
T2	511583	2757	0	0
T3	38896	0	0	0
T5	9967	0	0	0
T6	24080	0	0	0
T7	1520	0	0	0
T8	158	0	0	0
T9	368425	3357	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T14	0	18137	0	0
T24	0	264	0	0
T25	0	19218	0	0
T27	0	269	0	0
T33	0	6616	0	0
T34	0	1182	0	0
T36	0	5589	0	0
T37	0	1551	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	856287	0	0
T2	511583	2757	0	0
T3	38896	0	0	0
T5	9967	0	0	0
T6	24080	0	0	0
T7	1520	0	0	0
T8	158	0	0	0
T9	368425	3357	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T14	0	18137	0	0
T24	0	264	0	0
T25	0	19218	0	0
T27	0	269	0	0
T33	0	6616	0	0
T34	0	1182	0	0
T36	0	5589	0	0
T37	0	1551	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	856287	0	0
T2	511583	2757	0	0
T3	38896	0	0	0
T5	9967	0	0	0
T6	24080	0	0	0
T7	1520	0	0	0
T8	158	0	0	0
T9	368425	3357	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T14	0	18137	0	0
T24	0	264	0	0
T25	0	19218	0	0
T27	0	269	0	0
T33	0	6616	0	0
T34	0	1182	0	0
T36	0	5589	0	0
T37	0	1551	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	116032670	0	0
T1	26738	26738	0	0
T2	511583	510473	0	0
T3	38896	38896	0	0
T5	9967	9967	0	0
T6	24080	24080	0	0
T7	1520	0	0	0
T8	158	158	0	0
T9	368425	366669	0	0
T10	95648	95028	0	0
T11	576	0	0	0
T12	0	8000	0	0
T13	0	47744	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142468188	856287	0	0
T2	511583	2757	0	0
T3	38896	0	0	0
T5	9967	0	0	0
T6	24080	0	0	0
T7	1520	0	0	0
T8	158	0	0	0
T9	368425	3357	0	0
T10	95648	0	0	0
T11	576	0	0	0
T12	8000	0	0	0
T14	0	18137	0	0
T24	0	264	0	0
T25	0	19218	0	0
T27	0	269	0	0
T33	0	6616	0	0
T34	0	1182	0	0
T36	0	5589	0	0
T37	0	1551	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	451501096	451416297	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	451501096	2186999	0	0
GntImpliesValid_A	451501096	2186999	0	0
GrantKnown_A	451501096	451416297	0	0
IdxKnown_A	451501096	451416297	0	0
IndexIsCorrect_A	451501096	2186999	0	0
LockArbDecision_A	451501096	0	0	0
NoReadyValidNoGrant_A	451501096	0	0	0
ReadyAndValidImplyGrant_A	451501096	2186999	0	0
ReqAndReadyImplyGrant_A	451501096	2186999	0	0
ReqImpliesValid_A	451501096	2186999	0	0
ReqStaysHighUntilGranted0_M	451501096	0	0	0
RoundRobin_A	451501096	4	0	956
ValidKnown_A	451501096	451416297	0	0
gen_data_port_assertion.DataFlow_A	451501096	2186999	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	451416297	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	2186999	0	0
T1	11858	832	0	0
T2	213499	5898	0	0
T3	23360	832	0	0
T4	1548	0	0	0
T5	72909	832	0	0
T6	172193	832	0	0
T7	3078	34	0	0
T8	6511	832	0	0
T9	298607	9627	0	0
T10	200133	832	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	2186999	0	0
T1	11858	832	0	0
T2	213499	5898	0	0
T3	23360	832	0	0
T4	1548	0	0	0
T5	72909	832	0	0
T6	172193	832	0	0
T7	3078	34	0	0
T8	6511	832	0	0
T9	298607	9627	0	0
T10	200133	832	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	451416297	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	451416297	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	2186999	0	0
T1	11858	832	0	0
T2	213499	5898	0	0
T3	23360	832	0	0
T4	1548	0	0	0
T5	72909	832	0	0
T6	172193	832	0	0
T7	3078	34	0	0
T8	6511	832	0	0
T9	298607	9627	0	0
T10	200133	832	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	2186999	0	0
T1	11858	832	0	0
T2	213499	5898	0	0
T3	23360	832	0	0
T4	1548	0	0	0
T5	72909	832	0	0
T6	172193	832	0	0
T7	3078	34	0	0
T8	6511	832	0	0
T9	298607	9627	0	0
T10	200133	832	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	2186999	0	0
T1	11858	832	0	0
T2	213499	5898	0	0
T3	23360	832	0	0
T4	1548	0	0	0
T5	72909	832	0	0
T6	172193	832	0	0
T7	3078	34	0	0
T8	6511	832	0	0
T9	298607	9627	0	0
T10	200133	832	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	2186999	0	0
T1	11858	832	0	0
T2	213499	5898	0	0
T3	23360	832	0	0
T4	1548	0	0	0
T5	72909	832	0	0
T6	172193	832	0	0
T7	3078	34	0	0
T8	6511	832	0	0
T9	298607	9627	0	0
T10	200133	832	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	4	0	956
T54	558612	1	0	1
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	1405	0	0	1
T59	158681	0	0	1
T60	28825	0	0	1
T61	472722	0	0	1
T62	4572	0	0	1
T63	252295	0	0	1
T64	794396	0	0	1
T65	379400	0	0	1
T66	1624	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	451416297	0	0
T1	11858	11793	0	0
T2	213499	213433	0	0
T3	23360	23273	0	0
T4	1548	1464	0	0
T5	72909	72813	0	0
T6	172193	172120	0	0
T7	3078	2981	0	0
T8	6511	6446	0	0
T9	298607	298597	0	0
T10	200133	200049	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451501096	2186999	0	0
T1	11858	832	0	0
T2	213499	5898	0	0
T3	23360	832	0	0
T4	1548	0	0	0
T5	72909	832	0	0
T6	172193	832	0	0
T7	3078	34	0	0
T8	6511	832	0	0
T9	298607	9627	0	0
T10	200133	832	0	0
T12	0	832	0	0