Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3325004	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4193812

1

T1

1463

T2

877

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4141120	1			T1	1244		T2	3		T3	1
values[0x0]	1687781	1			T1	449		T2	479		T3	2
values[0x1]	1689915	1			T1	439		T2	398		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2377343	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5141473

1

T1

1596

T2

878

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28437	1			T2	7		T4	45		T6	3
valid_sources[0x01]	26096	1			T2	3		T4	51		T7	82
valid_sources[0x02]	32418	1			T4	37		T7	3		T10	6
valid_sources[0x03]	28365	1			T2	1		T4	47		T10	7
valid_sources[0x04]	29510	1			T2	3		T4	57		T6	1
valid_sources[0x05]	29709	1			T2	1		T4	40		T10	20
valid_sources[0x06]	32961	1			T2	4		T4	48		T6	1
valid_sources[0x07]	26177	1			T2	2		T4	35		T6	1
valid_sources[0x08]	29674	1			T4	46		T6	1		T7	80
valid_sources[0x09]	29815	1			T2	2		T4	44		T7	143
valid_sources[0x0a]	29147	1			T2	5		T4	50		T7	230
valid_sources[0x0b]	25966	1			T2	10		T4	46		T6	1
valid_sources[0x0c]	27929	1			T2	6		T4	45		T7	98
valid_sources[0x0d]	27501	1			T2	2		T4	40		T6	1
valid_sources[0x0e]	26111	1			T2	3		T4	25		T7	8
valid_sources[0x0f]	30165	1			T2	3		T4	38		T6	1
valid_sources[0x10]	27845	1			T2	6		T4	42		T11	6
valid_sources[0x11]	30109	1			T2	1		T4	33		T6	2
valid_sources[0x12]	27429	1			T2	4		T4	48		T10	3
valid_sources[0x13]	30909	1			T2	6		T4	36		T6	4
valid_sources[0x14]	29136	1			T2	3		T4	29		T7	1
valid_sources[0x15]	34282	1			T2	7		T4	43		T7	1
valid_sources[0x16]	26984	1			T2	6		T4	51		T7	190
valid_sources[0x17]	28626	1			T2	1		T4	46		T7	33
valid_sources[0x18]	32202	1			T2	2		T4	42		T10	19
valid_sources[0x19]	28337	1			T4	49		T7	35		T10	3
valid_sources[0x1a]	26980	1			T2	1		T4	30		T8	1
valid_sources[0x1b]	30572	1			T2	3		T4	31		T5	1
valid_sources[0x1c]	28115	1			T2	3		T4	46		T6	2
valid_sources[0x1d]	28006	1			T2	4		T4	41		T7	54
valid_sources[0x1e]	31103	1			T2	2		T4	44		T10	30
valid_sources[0x1f]	28233	1			T2	2		T4	48		T10	1
valid_sources[0x20]	29206	1			T2	2		T4	45		T6	2
valid_sources[0x21]	29110	1			T4	42		T6	1		T7	4
valid_sources[0x22]	27867	1			T2	4		T4	41		T6	1
valid_sources[0x23]	28408	1			T2	3		T4	48		T6	4
valid_sources[0x24]	29472	1			T2	8		T4	55		T11	8
valid_sources[0x25]	28038	1			T2	1		T4	50		T7	60
valid_sources[0x26]	27635	1			T2	6		T4	37		T6	3
valid_sources[0x27]	29509	1			T2	2		T4	41		T7	186
valid_sources[0x28]	29819	1			T2	5		T4	33		T6	1
valid_sources[0x29]	33130	1			T2	4		T4	45		T6	3
valid_sources[0x2a]	29947	1			T2	1		T4	50		T7	122
valid_sources[0x2b]	29396	1			T2	4		T4	53		T6	1
valid_sources[0x2c]	29334	1			T2	1		T4	45		T6	1
valid_sources[0x2d]	27455	1			T2	4		T4	41		T6	1
valid_sources[0x2e]	27909	1			T2	3		T4	40		T6	2
valid_sources[0x2f]	31731	1			T2	3		T4	37		T6	3
valid_sources[0x30]	26242	1			T2	5		T4	41		T6	1
valid_sources[0x31]	27000	1			T2	3		T4	50		T6	2
valid_sources[0x32]	27474	1			T2	11		T4	47		T6	3
valid_sources[0x33]	28160	1			T2	1		T4	42		T6	1
valid_sources[0x34]	38123	1			T2	4		T4	48		T6	5
valid_sources[0x35]	28165	1			T2	7		T4	46		T6	1
valid_sources[0x36]	31815	1			T2	2		T4	50		T6	1
valid_sources[0x37]	28795	1			T2	1		T4	41		T6	2
valid_sources[0x38]	29031	1			T2	1		T4	44		T11	8
valid_sources[0x39]	33320	1			T2	4		T4	60		T6	2
valid_sources[0x3a]	29532	1			T2	5		T4	30		T7	345
valid_sources[0x3b]	30395	1			T2	3		T4	50		T6	1
valid_sources[0x3c]	32237	1			T2	3		T4	60		T6	1
valid_sources[0x3d]	27565	1			T2	7		T4	38		T7	3
valid_sources[0x3e]	29854	1			T2	1		T4	47		T7	18
valid_sources[0x3f]	29054	1			T4	37		T6	1		T10	19
valid_sources[0x40]	26320	1			T2	1		T4	43		T7	60
valid_sources[0x41]	27740	1			T2	1		T4	35		T7	4
valid_sources[0x42]	28693	1			T2	4		T4	38		T6	2
valid_sources[0x43]	26749	1			T4	36		T7	11		T11	2
valid_sources[0x44]	30081	1			T2	2		T4	49		T6	2
valid_sources[0x45]	31066	1			T2	2		T4	49		T7	1
valid_sources[0x46]	25884	1			T2	3		T4	39		T6	2
valid_sources[0x47]	26862	1			T4	36		T7	73		T8	1
valid_sources[0x48]	27523	1			T2	2		T4	45		T6	3
valid_sources[0x49]	27301	1			T2	4		T4	54		T7	51
valid_sources[0x4a]	26767	1			T2	5		T4	35		T7	1
valid_sources[0x4b]	26973	1			T2	3		T4	37		T6	1
valid_sources[0x4c]	27642	1			T2	4		T4	42		T6	1
valid_sources[0x4d]	28270	1			T2	1		T4	39		T6	1
valid_sources[0x4e]	28755	1			T2	1		T4	48		T7	15
valid_sources[0x4f]	26855	1			T4	55		T6	1		T7	4
valid_sources[0x50]	30106	1			T2	2		T4	39		T6	1
valid_sources[0x51]	30738	1			T2	2		T4	49		T6	2
valid_sources[0x52]	25690	1			T2	2		T4	58		T7	65
valid_sources[0x53]	26376	1			T1	8		T2	4		T4	46
valid_sources[0x54]	30673	1			T2	1		T4	45		T6	4
valid_sources[0x55]	27680	1			T4	39		T6	1		T7	75
valid_sources[0x56]	26456	1			T2	3		T4	54		T7	4
valid_sources[0x57]	26636	1			T2	4		T4	30		T7	2
valid_sources[0x58]	31447	1			T2	5		T4	52		T6	1
valid_sources[0x59]	28703	1			T2	3		T4	43		T7	14
valid_sources[0x5a]	30070	1			T2	4		T4	52		T7	499
valid_sources[0x5b]	28647	1			T2	5		T4	48		T6	5
valid_sources[0x5c]	27985	1			T4	40		T6	1		T7	125
valid_sources[0x5d]	29763	1			T2	3		T4	44		T6	1
valid_sources[0x5e]	29631	1			T2	5		T4	41		T6	3
valid_sources[0x5f]	35134	1			T2	7		T4	35		T7	124
valid_sources[0x60]	37843	1			T2	2		T4	43		T6	1
valid_sources[0x61]	27313	1			T2	2		T4	45		T7	78
valid_sources[0x62]	27524	1			T4	37		T6	1		T7	16
valid_sources[0x63]	29536	1			T4	40		T6	2		T7	33
valid_sources[0x64]	31811	1			T2	8		T4	46		T7	3
valid_sources[0x65]	27133	1			T1	627		T2	2		T4	45
valid_sources[0x66]	30850	1			T2	9		T4	40		T7	72
valid_sources[0x67]	27784	1			T4	37		T10	16		T14	257
valid_sources[0x68]	28657	1			T2	7		T4	52		T7	2
valid_sources[0x69]	30772	1			T2	7		T4	30		T7	110
valid_sources[0x6a]	32731	1			T4	46		T7	229		T11	2
valid_sources[0x6b]	28164	1			T2	1		T4	39		T6	1
valid_sources[0x6c]	28122	1			T2	3		T4	48		T6	1
valid_sources[0x6d]	26792	1			T2	6		T4	42		T6	1
valid_sources[0x6e]	28835	1			T2	6		T4	50		T7	2
valid_sources[0x6f]	30558	1			T2	6		T4	66		T7	9
valid_sources[0x70]	28642	1			T2	3		T4	48		T6	1
valid_sources[0x71]	28356	1			T2	6		T4	49		T6	1
valid_sources[0x72]	29718	1			T2	1		T4	41		T6	2
valid_sources[0x73]	29663	1			T2	4		T4	41		T7	26
valid_sources[0x74]	28776	1			T2	4		T4	40		T10	14
valid_sources[0x75]	26183	1			T2	4		T4	36		T6	4
valid_sources[0x76]	27170	1			T2	5		T4	43		T7	16
valid_sources[0x77]	33397	1			T2	5		T4	39		T6	2
valid_sources[0x78]	26876	1			T4	44		T6	2		T7	79
valid_sources[0x79]	36963	1			T2	6		T4	55		T5	7707
valid_sources[0x7a]	28624	1			T4	35		T10	10		T11	5
valid_sources[0x7b]	27478	1			T2	1		T4	52		T7	2
valid_sources[0x7c]	27620	1			T2	2		T4	52		T6	1
valid_sources[0x7d]	27709	1			T2	1		T4	36		T6	1
valid_sources[0x7e]	33303	1			T2	9		T3	8		T4	41
valid_sources[0x7f]	27199	1			T2	3		T4	36		T7	1
valid_sources[0x80]	29824	1			T2	4		T4	37		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1115269

1

T1

588

T2

2

T3

1

values[0x0]

all_enables

biggest_size

1549599

1

T1

445

T2

477

T3

2

values[0x1]

all_enables

biggest_size

1528944

1

T1

430

T2

398

T4

3867