Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3353151

1

T1

669

T2

3

T3

5

full_word

4195563

1

T1

1463

T2

877

T3

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7548394	1			T1	2132		T2	880		T3	8
auto[TlIntgErrCmd]	115	1			T92	3		T94	4		T95	4
auto[TlIntgErrData]	92	1			T92	2		T94	2		T95	2
auto[TlIntgErrBoth]	113	1			T92	5		T94	4		T95	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4148032

1

T1

1244

T2

3

T3

1

auto[1]

3400682

1

T1

888

T2

877

T3

7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3032120	1			T1	656		T2	1		T4	1406
auto[TlIntgErrNone]	partial	auto[1]	320733	1			T1	13		T2	2		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	1115771	1			T1	588		T2	2		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3079770	1			T1	875		T2	875		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T92	1		T94	1		T95	3
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T92	2		T94	3		T95	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T107	1		T141	1		T167	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T141	1		T146	1		T168	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T92	1		T94	1		T95	1
auto[TlIntgErrData]	partial	auto[1]	39	1			T92	1		T94	1		T106	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T141	1		T167	1		T162	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T95	1		T163	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T92	1		T95	3		T106	2
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T92	3		T94	3		T95	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T92	1		T94	1		T169	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T141	1		T146	1		T162	1