Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	594575891	3291376	0	0
gen_wmask[1].MaskCheckPortA_A	594575891	3291376	0	0
gen_wmask[2].MaskCheckPortA_A	594575891	3291376	0	0
gen_wmask[3].MaskCheckPortA_A	594575891	3291376	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594575891	3291376	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	578220	13615	0	0
T5	268800	832	0	0
T6	132375	0	0	0
T7	904493	3587	0	0
T8	2064	10	0	0
T9	133833	832	0	0
T10	855912	8361	0	0
T11	18276	832	0	0
T14	840086	17842	0	0
T15	86327	0	0	0
T16	0	10589	0	0
T24	0	1390	0	0
T25	0	420	0	0
T28	0	2273	0	0
T35	0	6253	0	0
T39	0	12	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594575891	3291376	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	578220	13615	0	0
T5	268800	832	0	0
T6	132375	0	0	0
T7	904493	3587	0	0
T8	2064	10	0	0
T9	133833	832	0	0
T10	855912	8361	0	0
T11	18276	832	0	0
T14	840086	17842	0	0
T15	86327	0	0	0
T16	0	10589	0	0
T24	0	1390	0	0
T25	0	420	0	0
T28	0	2273	0	0
T35	0	6253	0	0
T39	0	12	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594575891	3291376	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	578220	13615	0	0
T5	268800	832	0	0
T6	132375	0	0	0
T7	904493	3587	0	0
T8	2064	10	0	0
T9	133833	832	0	0
T10	855912	8361	0	0
T11	18276	832	0	0
T14	840086	17842	0	0
T15	86327	0	0	0
T16	0	10589	0	0
T24	0	1390	0	0
T25	0	420	0	0
T28	0	2273	0	0
T35	0	6253	0	0
T39	0	12	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594575891	3291376	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	578220	13615	0	0
T5	268800	832	0	0
T6	132375	0	0	0
T7	904493	3587	0	0
T8	2064	10	0	0
T9	133833	832	0	0
T10	855912	8361	0	0
T11	18276	832	0	0
T14	840086	17842	0	0
T15	86327	0	0	0
T16	0	10589	0	0
T24	0	1390	0	0
T25	0	420	0	0
T28	0	2273	0	0
T35	0	6253	0	0
T39	0	12	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	447957080	2082725	0	0
gen_wmask[1].MaskCheckPortA_A	447957080	2082725	0	0
gen_wmask[2].MaskCheckPortA_A	447957080	2082725	0	0
gen_wmask[3].MaskCheckPortA_A	447957080	2082725	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	2082725	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	196040	7488	0	0
T5	101137	832	0	0
T6	43860	0	0	0
T7	775133	1248	0	0
T8	1608	10	0	0
T9	33600	832	0	0
T10	714182	1664	0	0
T11	0	832	0	0
T14	0	9617	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	2082725	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	196040	7488	0	0
T5	101137	832	0	0
T6	43860	0	0	0
T7	775133	1248	0	0
T8	1608	10	0	0
T9	33600	832	0	0
T10	714182	1664	0	0
T11	0	832	0	0
T14	0	9617	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	2082725	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	196040	7488	0	0
T5	101137	832	0	0
T6	43860	0	0	0
T7	775133	1248	0	0
T8	1608	10	0	0
T9	33600	832	0	0
T10	714182	1664	0	0
T11	0	832	0	0
T14	0	9617	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	2082725	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	196040	7488	0	0
T5	101137	832	0	0
T6	43860	0	0	0
T7	775133	1248	0	0
T8	1608	10	0	0
T9	33600	832	0	0
T10	714182	1664	0	0
T11	0	832	0	0
T14	0	9617	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T10
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	146618811	1208651	0	0
gen_wmask[1].MaskCheckPortA_A	146618811	1208651	0	0
gen_wmask[2].MaskCheckPortA_A	146618811	1208651	0	0
gen_wmask[3].MaskCheckPortA_A	146618811	1208651	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	1208651	0	0
T4	382180	6127	0	0
T5	167663	0	0	0
T6	88515	0	0	0
T7	129360	2339	0	0
T8	456	0	0	0
T9	100233	0	0	0
T10	141730	6697	0	0
T11	18276	0	0	0
T14	840086	8225	0	0
T15	86327	0	0	0
T16	0	10589	0	0
T24	0	1390	0	0
T25	0	420	0	0
T28	0	2273	0	0
T35	0	6253	0	0
T39	0	12	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	1208651	0	0
T4	382180	6127	0	0
T5	167663	0	0	0
T6	88515	0	0	0
T7	129360	2339	0	0
T8	456	0	0	0
T9	100233	0	0	0
T10	141730	6697	0	0
T11	18276	0	0	0
T14	840086	8225	0	0
T15	86327	0	0	0
T16	0	10589	0	0
T24	0	1390	0	0
T25	0	420	0	0
T28	0	2273	0	0
T35	0	6253	0	0
T39	0	12	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	1208651	0	0
T4	382180	6127	0	0
T5	167663	0	0	0
T6	88515	0	0	0
T7	129360	2339	0	0
T8	456	0	0	0
T9	100233	0	0	0
T10	141730	6697	0	0
T11	18276	0	0	0
T14	840086	8225	0	0
T15	86327	0	0	0
T16	0	10589	0	0
T24	0	1390	0	0
T25	0	420	0	0
T28	0	2273	0	0
T35	0	6253	0	0
T39	0	12	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	1208651	0	0
T4	382180	6127	0	0
T5	167663	0	0	0
T6	88515	0	0	0
T7	129360	2339	0	0
T8	456	0	0	0
T9	100233	0	0	0
T10	141730	6697	0	0
T11	18276	0	0	0
T14	840086	8225	0	0
T15	86327	0	0	0
T16	0	10589	0	0
T24	0	1390	0	0
T25	0	420	0	0
T28	0	2273	0	0
T35	0	6253	0	0
T39	0	12	0	0