Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T14,T24
1	0	Covered	T7,T8,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Covered	T7,T8,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T7,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T4,T7,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	741194702	593136928	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	741194702	3668249	0	0
GntImpliesValid_A	741194702	3668249	0	0
GrantKnown_A	741194702	593136928	0	0
IdxKnown_A	741194702	593136928	0	0
IndexIsCorrect_A	741194702	3668249	0	0
LockArbDecision_A	741194702	0	0	0
NoReadyValidNoGrant_A	741194702	0	0	0
ReadyAndValidImplyGrant_A	741194702	3668249	0	0
ReqAndReadyImplyGrant_A	741194702	3668249	0	0
ReqImpliesValid_A	741194702	3668249	0	0
ReqStaysHighUntilGranted0_M	741194702	0	0	0
RoundRobin_A	741194702	4	0	956
ValidKnown_A	741194702	593136928	0	0
gen_data_port_assertion.DataFlow_A	741194702	3668249	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741194702	593136928	0	0
T1	58155	57805	0	0
T2	188708	188643	0	0
T3	937	855	0	0
T4	578220	575586	0	0
T5	268800	268363	0	0
T6	220890	127644	0	0
T7	1033853	901891	0	0
T8	2520	1987	0	0
T9	234066	133584	0	0
T10	997642	855476	0	0
T11	36552	18276	0	0
T14	840086	836165	0	0
T15	86327	85844	0	0
T23	19334	0	0	0
T24	0	158192	0	0
T25	0	21792	0	0
T26	0	48616	0	0
T27	0	72	0	0
T28	0	333536	0	0
T29	0	21584	0	0
T40	95438	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741194702	3668249	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	578220	13960	0	0
T5	268800	832	0	0
T6	132375	0	0	0
T7	1033853	4576	0	0
T8	2520	21	0	0
T9	234066	832	0	0
T10	997642	8660	0	0
T11	36552	832	0	0
T14	1680172	19020	0	0
T15	172654	0	0	0
T16	0	13346	0	0
T23	19334	0	0	0
T24	0	2457	0	0
T25	0	819	0	0
T28	0	3421	0	0
T30	0	11867	0	0
T35	0	6253	0	0
T39	98396	12	0	0
T40	95438	0	0	0
T41	0	2610	0	0
T47	0	1443	0	0
T48	0	4350	0	0
T49	0	6657	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741194702	3668249	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	578220	13960	0	0
T5	268800	832	0	0
T6	132375	0	0	0
T7	1033853	4576	0	0
T8	2520	21	0	0
T9	234066	832	0	0
T10	997642	8660	0	0
T11	36552	832	0	0
T14	1680172	19020	0	0
T15	172654	0	0	0
T16	0	13346	0	0
T23	19334	0	0	0
T24	0	2457	0	0
T25	0	819	0	0
T28	0	3421	0	0
T30	0	11867	0	0
T35	0	6253	0	0
T39	98396	12	0	0
T40	95438	0	0	0
T41	0	2610	0	0
T47	0	1443	0	0
T48	0	4350	0	0
T49	0	6657	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741194702	593136928	0	0
T1	58155	57805	0	0
T2	188708	188643	0	0
T3	937	855	0	0
T4	578220	575586	0	0
T5	268800	268363	0	0
T6	220890	127644	0	0
T7	1033853	901891	0	0
T8	2520	1987	0	0
T9	234066	133584	0	0
T10	997642	855476	0	0
T11	36552	18276	0	0
T14	840086	836165	0	0
T15	86327	85844	0	0
T23	19334	0	0	0
T24	0	158192	0	0
T25	0	21792	0	0
T26	0	48616	0	0
T27	0	72	0	0
T28	0	333536	0	0
T29	0	21584	0	0
T40	95438	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741194702	593136928	0	0
T1	58155	57805	0	0
T2	188708	188643	0	0
T3	937	855	0	0
T4	578220	575586	0	0
T5	268800	268363	0	0
T6	220890	127644	0	0
T7	1033853	901891	0	0
T8	2520	1987	0	0
T9	234066	133584	0	0
T10	997642	855476	0	0
T11	36552	18276	0	0
T14	840086	836165	0	0
T15	86327	85844	0	0
T23	19334	0	0	0
T24	0	158192	0	0
T25	0	21792	0	0
T26	0	48616	0	0
T27	0	72	0	0
T28	0	333536	0	0
T29	0	21584	0	0
T40	95438	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741194702	3668249	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	578220	13960	0	0
T5	268800	832	0	0
T6	132375	0	0	0
T7	1033853	4576	0	0
T8	2520	21	0	0
T9	234066	832	0	0
T10	997642	8660	0	0
T11	36552	832	0	0
T14	1680172	19020	0	0
T15	172654	0	0	0
T16	0	13346	0	0
T23	19334	0	0	0
T24	0	2457	0	0
T25	0	819	0	0
T28	0	3421	0	0
T30	0	11867	0	0
T35	0	6253	0	0
T39	98396	12	0	0
T40	95438	0	0	0
T41	0	2610	0	0
T47	0	1443	0	0
T48	0	4350	0	0
T49	0	6657	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741194702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741194702	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741194702	3668249	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	578220	13960	0	0
T5	268800	832	0	0
T6	132375	0	0	0
T7	1033853	4576	0	0
T8	2520	21	0	0
T9	234066	832	0	0
T10	997642	8660	0	0
T11	36552	832	0	0
T14	1680172	19020	0	0
T15	172654	0	0	0
T16	0	13346	0	0
T23	19334	0	0	0
T24	0	2457	0	0
T25	0	819	0	0
T28	0	3421	0	0
T30	0	11867	0	0
T35	0	6253	0	0
T39	98396	12	0	0
T40	95438	0	0	0
T41	0	2610	0	0
T47	0	1443	0	0
T48	0	4350	0	0
T49	0	6657	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741194702	3668249	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	578220	13960	0	0
T5	268800	832	0	0
T6	132375	0	0	0
T7	1033853	4576	0	0
T8	2520	21	0	0
T9	234066	832	0	0
T10	997642	8660	0	0
T11	36552	832	0	0
T14	1680172	19020	0	0
T15	172654	0	0	0
T16	0	13346	0	0
T23	19334	0	0	0
T24	0	2457	0	0
T25	0	819	0	0
T28	0	3421	0	0
T30	0	11867	0	0
T35	0	6253	0	0
T39	98396	12	0	0
T40	95438	0	0	0
T41	0	2610	0	0
T47	0	1443	0	0
T48	0	4350	0	0
T49	0	6657	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741194702	3668249	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	578220	13960	0	0
T5	268800	832	0	0
T6	132375	0	0	0
T7	1033853	4576	0	0
T8	2520	21	0	0
T9	234066	832	0	0
T10	997642	8660	0	0
T11	36552	832	0	0
T14	1680172	19020	0	0
T15	172654	0	0	0
T16	0	13346	0	0
T23	19334	0	0	0
T24	0	2457	0	0
T25	0	819	0	0
T28	0	3421	0	0
T30	0	11867	0	0
T35	0	6253	0	0
T39	98396	12	0	0
T40	95438	0	0	0
T41	0	2610	0	0
T47	0	1443	0	0
T48	0	4350	0	0
T49	0	6657	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	741194702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741194702	4	0	956
T33	291639	1	0	1
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	1912	0	0	1
T54	31276	0	0	1
T55	32857	0	0	1
T56	30993	0	0	1
T57	2723	0	0	1
T58	180273	0	0	1
T59	576272	0	0	1
T60	628386	0	0	1
T61	157111	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741194702	593136928	0	0
T1	58155	57805	0	0
T2	188708	188643	0	0
T3	937	855	0	0
T4	578220	575586	0	0
T5	268800	268363	0	0
T6	220890	127644	0	0
T7	1033853	901891	0	0
T8	2520	1987	0	0
T9	234066	133584	0	0
T10	997642	855476	0	0
T11	36552	18276	0	0
T14	840086	836165	0	0
T15	86327	85844	0	0
T23	19334	0	0	0
T24	0	158192	0	0
T25	0	21792	0	0
T26	0	48616	0	0
T27	0	72	0	0
T28	0	333536	0	0
T29	0	21584	0	0
T40	95438	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741194702	3668249	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	578220	13960	0	0
T5	268800	832	0	0
T6	132375	0	0	0
T7	1033853	4576	0	0
T8	2520	21	0	0
T9	234066	832	0	0
T10	997642	8660	0	0
T11	36552	832	0	0
T14	1680172	19020	0	0
T15	172654	0	0	0
T16	0	13346	0	0
T23	19334	0	0	0
T24	0	2457	0	0
T25	0	819	0	0
T28	0	3421	0	0
T30	0	11867	0	0
T35	0	6253	0	0
T39	98396	12	0	0
T40	95438	0	0	0
T41	0	2610	0	0
T47	0	1443	0	0
T48	0	4350	0	0
T49	0	6657	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T14,T24
1	0	Covered	T7,T8,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Covered	T7,T8,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T8,T14
0	0	1	Unreachable
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	146618811	29099528	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	146618811	612426	0	0
GntImpliesValid_A	146618811	612426	0	0
GrantKnown_A	146618811	29099528	0	0
IdxKnown_A	146618811	29099528	0	0
IndexIsCorrect_A	146618811	612426	0	0
LockArbDecision_A	146618811	0	0	0
NoReadyValidNoGrant_A	146618811	0	0	0
ReadyAndValidImplyGrant_A	146618811	612426	0	0
ReqAndReadyImplyGrant_A	146618811	612426	0	0
ReqImpliesValid_A	146618811	612426	0	0
ReqStaysHighUntilGranted0_M	146618811	0	0	0
RoundRobin_A	146618811	0	0	0
ValidKnown_A	146618811	29099528	0	0
gen_data_port_assertion.DataFlow_A	146618811	612426	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	29099528	0	0
T6	88515	83840	0	0
T7	129360	47664	0	0
T8	456	456	0	0
T9	100233	0	0	0
T10	141730	0	0	0
T11	18276	0	0	0
T14	840086	37536	0	0
T15	86327	0	0	0
T23	19334	0	0	0
T24	0	158192	0	0
T25	0	21792	0	0
T26	0	48616	0	0
T27	0	72	0	0
T28	0	333536	0	0
T29	0	21584	0	0
T40	95438	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	612426	0	0
T7	129360	2105	0	0
T8	456	11	0	0
T9	100233	0	0	0
T10	141730	0	0	0
T11	18276	0	0	0
T14	840086	1800	0	0
T15	86327	0	0	0
T16	0	7781	0	0
T23	19334	0	0	0
T24	0	2457	0	0
T25	0	819	0	0
T28	0	3421	0	0
T30	0	4954	0	0
T39	98396	0	0	0
T40	95438	0	0	0
T41	0	2610	0	0
T47	0	1443	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	612426	0	0
T7	129360	2105	0	0
T8	456	11	0	0
T9	100233	0	0	0
T10	141730	0	0	0
T11	18276	0	0	0
T14	840086	1800	0	0
T15	86327	0	0	0
T16	0	7781	0	0
T23	19334	0	0	0
T24	0	2457	0	0
T25	0	819	0	0
T28	0	3421	0	0
T30	0	4954	0	0
T39	98396	0	0	0
T40	95438	0	0	0
T41	0	2610	0	0
T47	0	1443	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	29099528	0	0
T6	88515	83840	0	0
T7	129360	47664	0	0
T8	456	456	0	0
T9	100233	0	0	0
T10	141730	0	0	0
T11	18276	0	0	0
T14	840086	37536	0	0
T15	86327	0	0	0
T23	19334	0	0	0
T24	0	158192	0	0
T25	0	21792	0	0
T26	0	48616	0	0
T27	0	72	0	0
T28	0	333536	0	0
T29	0	21584	0	0
T40	95438	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	29099528	0	0
T6	88515	83840	0	0
T7	129360	47664	0	0
T8	456	456	0	0
T9	100233	0	0	0
T10	141730	0	0	0
T11	18276	0	0	0
T14	840086	37536	0	0
T15	86327	0	0	0
T23	19334	0	0	0
T24	0	158192	0	0
T25	0	21792	0	0
T26	0	48616	0	0
T27	0	72	0	0
T28	0	333536	0	0
T29	0	21584	0	0
T40	95438	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	612426	0	0
T7	129360	2105	0	0
T8	456	11	0	0
T9	100233	0	0	0
T10	141730	0	0	0
T11	18276	0	0	0
T14	840086	1800	0	0
T15	86327	0	0	0
T16	0	7781	0	0
T23	19334	0	0	0
T24	0	2457	0	0
T25	0	819	0	0
T28	0	3421	0	0
T30	0	4954	0	0
T39	98396	0	0	0
T40	95438	0	0	0
T41	0	2610	0	0
T47	0	1443	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	612426	0	0
T7	129360	2105	0	0
T8	456	11	0	0
T9	100233	0	0	0
T10	141730	0	0	0
T11	18276	0	0	0
T14	840086	1800	0	0
T15	86327	0	0	0
T16	0	7781	0	0
T23	19334	0	0	0
T24	0	2457	0	0
T25	0	819	0	0
T28	0	3421	0	0
T30	0	4954	0	0
T39	98396	0	0	0
T40	95438	0	0	0
T41	0	2610	0	0
T47	0	1443	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	612426	0	0
T7	129360	2105	0	0
T8	456	11	0	0
T9	100233	0	0	0
T10	141730	0	0	0
T11	18276	0	0	0
T14	840086	1800	0	0
T15	86327	0	0	0
T16	0	7781	0	0
T23	19334	0	0	0
T24	0	2457	0	0
T25	0	819	0	0
T28	0	3421	0	0
T30	0	4954	0	0
T39	98396	0	0	0
T40	95438	0	0	0
T41	0	2610	0	0
T47	0	1443	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	612426	0	0
T7	129360	2105	0	0
T8	456	11	0	0
T9	100233	0	0	0
T10	141730	0	0	0
T11	18276	0	0	0
T14	840086	1800	0	0
T15	86327	0	0	0
T16	0	7781	0	0
T23	19334	0	0	0
T24	0	2457	0	0
T25	0	819	0	0
T28	0	3421	0	0
T30	0	4954	0	0
T39	98396	0	0	0
T40	95438	0	0	0
T41	0	2610	0	0
T47	0	1443	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	29099528	0	0
T6	88515	83840	0	0
T7	129360	47664	0	0
T8	456	456	0	0
T9	100233	0	0	0
T10	141730	0	0	0
T11	18276	0	0	0
T14	840086	37536	0	0
T15	86327	0	0	0
T23	19334	0	0	0
T24	0	158192	0	0
T25	0	21792	0	0
T26	0	48616	0	0
T27	0	72	0	0
T28	0	333536	0	0
T29	0	21584	0	0
T40	95438	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	612426	0	0
T7	129360	2105	0	0
T8	456	11	0	0
T9	100233	0	0	0
T10	141730	0	0	0
T11	18276	0	0	0
T14	840086	1800	0	0
T15	86327	0	0	0
T16	0	7781	0	0
T23	19334	0	0	0
T24	0	2457	0	0
T25	0	819	0	0
T28	0	3421	0	0
T30	0	4954	0	0
T39	98396	0	0	0
T40	95438	0	0	0
T41	0	2610	0	0
T47	0	1443	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T10
1	0	Covered	T4,T7,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T4,T7,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T7,T10
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	146618811	116168305	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	146618811	798437	0	0
GntImpliesValid_A	146618811	798437	0	0
GrantKnown_A	146618811	116168305	0	0
IdxKnown_A	146618811	116168305	0	0
IndexIsCorrect_A	146618811	798437	0	0
LockArbDecision_A	146618811	0	0	0
NoReadyValidNoGrant_A	146618811	0	0	0
ReadyAndValidImplyGrant_A	146618811	798437	0	0
ReqAndReadyImplyGrant_A	146618811	798437	0	0
ReqImpliesValid_A	146618811	798437	0	0
ReqStaysHighUntilGranted0_M	146618811	0	0	0
RoundRobin_A	146618811	0	0	0
ValidKnown_A	146618811	116168305	0	0
gen_data_port_assertion.DataFlow_A	146618811	798437	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	116168305	0	0
T1	25984	25712	0	0
T2	25952	25952	0	0
T4	382180	379552	0	0
T5	167663	167232	0	0
T6	88515	0	0	0
T7	129360	79350	0	0
T8	456	0	0	0
T9	100233	100078	0	0
T10	141730	141385	0	0
T11	18276	18276	0	0
T14	0	798629	0	0
T15	0	85844	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	798437	0	0
T4	382180	6127	0	0
T5	167663	0	0	0
T6	88515	0	0	0
T7	129360	689	0	0
T8	456	0	0	0
T9	100233	0	0	0
T10	141730	6697	0	0
T11	18276	0	0	0
T14	840086	6936	0	0
T15	86327	0	0	0
T16	0	5565	0	0
T30	0	6913	0	0
T35	0	6253	0	0
T39	0	12	0	0
T48	0	4350	0	0
T49	0	6657	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	798437	0	0
T4	382180	6127	0	0
T5	167663	0	0	0
T6	88515	0	0	0
T7	129360	689	0	0
T8	456	0	0	0
T9	100233	0	0	0
T10	141730	6697	0	0
T11	18276	0	0	0
T14	840086	6936	0	0
T15	86327	0	0	0
T16	0	5565	0	0
T30	0	6913	0	0
T35	0	6253	0	0
T39	0	12	0	0
T48	0	4350	0	0
T49	0	6657	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	116168305	0	0
T1	25984	25712	0	0
T2	25952	25952	0	0
T4	382180	379552	0	0
T5	167663	167232	0	0
T6	88515	0	0	0
T7	129360	79350	0	0
T8	456	0	0	0
T9	100233	100078	0	0
T10	141730	141385	0	0
T11	18276	18276	0	0
T14	0	798629	0	0
T15	0	85844	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	116168305	0	0
T1	25984	25712	0	0
T2	25952	25952	0	0
T4	382180	379552	0	0
T5	167663	167232	0	0
T6	88515	0	0	0
T7	129360	79350	0	0
T8	456	0	0	0
T9	100233	100078	0	0
T10	141730	141385	0	0
T11	18276	18276	0	0
T14	0	798629	0	0
T15	0	85844	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	798437	0	0
T4	382180	6127	0	0
T5	167663	0	0	0
T6	88515	0	0	0
T7	129360	689	0	0
T8	456	0	0	0
T9	100233	0	0	0
T10	141730	6697	0	0
T11	18276	0	0	0
T14	840086	6936	0	0
T15	86327	0	0	0
T16	0	5565	0	0
T30	0	6913	0	0
T35	0	6253	0	0
T39	0	12	0	0
T48	0	4350	0	0
T49	0	6657	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	798437	0	0
T4	382180	6127	0	0
T5	167663	0	0	0
T6	88515	0	0	0
T7	129360	689	0	0
T8	456	0	0	0
T9	100233	0	0	0
T10	141730	6697	0	0
T11	18276	0	0	0
T14	840086	6936	0	0
T15	86327	0	0	0
T16	0	5565	0	0
T30	0	6913	0	0
T35	0	6253	0	0
T39	0	12	0	0
T48	0	4350	0	0
T49	0	6657	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	798437	0	0
T4	382180	6127	0	0
T5	167663	0	0	0
T6	88515	0	0	0
T7	129360	689	0	0
T8	456	0	0	0
T9	100233	0	0	0
T10	141730	6697	0	0
T11	18276	0	0	0
T14	840086	6936	0	0
T15	86327	0	0	0
T16	0	5565	0	0
T30	0	6913	0	0
T35	0	6253	0	0
T39	0	12	0	0
T48	0	4350	0	0
T49	0	6657	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	798437	0	0
T4	382180	6127	0	0
T5	167663	0	0	0
T6	88515	0	0	0
T7	129360	689	0	0
T8	456	0	0	0
T9	100233	0	0	0
T10	141730	6697	0	0
T11	18276	0	0	0
T14	840086	6936	0	0
T15	86327	0	0	0
T16	0	5565	0	0
T30	0	6913	0	0
T35	0	6253	0	0
T39	0	12	0	0
T48	0	4350	0	0
T49	0	6657	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	116168305	0	0
T1	25984	25712	0	0
T2	25952	25952	0	0
T4	382180	379552	0	0
T5	167663	167232	0	0
T6	88515	0	0	0
T7	129360	79350	0	0
T8	456	0	0	0
T9	100233	100078	0	0
T10	141730	141385	0	0
T11	18276	18276	0	0
T14	0	798629	0	0
T15	0	85844	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146618811	798437	0	0
T4	382180	6127	0	0
T5	167663	0	0	0
T6	88515	0	0	0
T7	129360	689	0	0
T8	456	0	0	0
T9	100233	0	0	0
T10	141730	6697	0	0
T11	18276	0	0	0
T14	840086	6936	0	0
T15	86327	0	0	0
T16	0	5565	0	0
T30	0	6913	0	0
T35	0	6253	0	0
T39	0	12	0	0
T48	0	4350	0	0
T49	0	6657	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	447957080	447869095	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	447957080	2257386	0	0
GntImpliesValid_A	447957080	2257386	0	0
GrantKnown_A	447957080	447869095	0	0
IdxKnown_A	447957080	447869095	0	0
IndexIsCorrect_A	447957080	2257386	0	0
LockArbDecision_A	447957080	0	0	0
NoReadyValidNoGrant_A	447957080	0	0	0
ReadyAndValidImplyGrant_A	447957080	2257386	0	0
ReqAndReadyImplyGrant_A	447957080	2257386	0	0
ReqImpliesValid_A	447957080	2257386	0	0
ReqStaysHighUntilGranted0_M	447957080	0	0	0
RoundRobin_A	447957080	4	0	956
ValidKnown_A	447957080	447869095	0	0
gen_data_port_assertion.DataFlow_A	447957080	2257386	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	447869095	0	0
T1	32171	32093	0	0
T2	162756	162691	0	0
T3	937	855	0	0
T4	196040	196034	0	0
T5	101137	101131	0	0
T6	43860	43804	0	0
T7	775133	774877	0	0
T8	1608	1531	0	0
T9	33600	33506	0	0
T10	714182	714091	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	2257386	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	196040	7833	0	0
T5	101137	832	0	0
T6	43860	0	0	0
T7	775133	1782	0	0
T8	1608	10	0	0
T9	33600	832	0	0
T10	714182	1963	0	0
T11	0	832	0	0
T14	0	10284	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	2257386	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	196040	7833	0	0
T5	101137	832	0	0
T6	43860	0	0	0
T7	775133	1782	0	0
T8	1608	10	0	0
T9	33600	832	0	0
T10	714182	1963	0	0
T11	0	832	0	0
T14	0	10284	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	447869095	0	0
T1	32171	32093	0	0
T2	162756	162691	0	0
T3	937	855	0	0
T4	196040	196034	0	0
T5	101137	101131	0	0
T6	43860	43804	0	0
T7	775133	774877	0	0
T8	1608	1531	0	0
T9	33600	33506	0	0
T10	714182	714091	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	447869095	0	0
T1	32171	32093	0	0
T2	162756	162691	0	0
T3	937	855	0	0
T4	196040	196034	0	0
T5	101137	101131	0	0
T6	43860	43804	0	0
T7	775133	774877	0	0
T8	1608	1531	0	0
T9	33600	33506	0	0
T10	714182	714091	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	2257386	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	196040	7833	0	0
T5	101137	832	0	0
T6	43860	0	0	0
T7	775133	1782	0	0
T8	1608	10	0	0
T9	33600	832	0	0
T10	714182	1963	0	0
T11	0	832	0	0
T14	0	10284	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	2257386	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	196040	7833	0	0
T5	101137	832	0	0
T6	43860	0	0	0
T7	775133	1782	0	0
T8	1608	10	0	0
T9	33600	832	0	0
T10	714182	1963	0	0
T11	0	832	0	0
T14	0	10284	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	2257386	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	196040	7833	0	0
T5	101137	832	0	0
T6	43860	0	0	0
T7	775133	1782	0	0
T8	1608	10	0	0
T9	33600	832	0	0
T10	714182	1963	0	0
T11	0	832	0	0
T14	0	10284	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	2257386	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	196040	7833	0	0
T5	101137	832	0	0
T6	43860	0	0	0
T7	775133	1782	0	0
T8	1608	10	0	0
T9	33600	832	0	0
T10	714182	1963	0	0
T11	0	832	0	0
T14	0	10284	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	4	0	956
T33	291639	1	0	1
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	1912	0	0	1
T54	31276	0	0	1
T55	32857	0	0	1
T56	30993	0	0	1
T57	2723	0	0	1
T58	180273	0	0	1
T59	576272	0	0	1
T60	628386	0	0	1
T61	157111	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	447869095	0	0
T1	32171	32093	0	0
T2	162756	162691	0	0
T3	937	855	0	0
T4	196040	196034	0	0
T5	101137	101131	0	0
T6	43860	43804	0	0
T7	775133	774877	0	0
T8	1608	1531	0	0
T9	33600	33506	0	0
T10	714182	714091	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447957080	2257386	0	0
T1	32171	832	0	0
T2	162756	832	0	0
T3	937	0	0	0
T4	196040	7833	0	0
T5	101137	832	0	0
T6	43860	0	0	0
T7	775133	1782	0	0
T8	1608	10	0	0
T9	33600	832	0	0
T10	714182	1963	0	0
T11	0	832	0	0
T14	0	10284	0	0