Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3871 |
0 |
0 |
T67 |
16085 |
286 |
0 |
0 |
T68 |
25296 |
252 |
0 |
0 |
T69 |
8960 |
93 |
0 |
0 |
T92 |
28336 |
1 |
0 |
0 |
T93 |
18940 |
332 |
0 |
0 |
T94 |
11716 |
2 |
0 |
0 |
T97 |
4998 |
140 |
0 |
0 |
T101 |
5196 |
18 |
0 |
0 |
T103 |
3750 |
9 |
0 |
0 |
T106 |
26373 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1226 |
0 |
0 |
T79 |
2844 |
1 |
0 |
0 |
T112 |
179743 |
423 |
0 |
0 |
T118 |
10455 |
3 |
0 |
0 |
T140 |
7974 |
29 |
0 |
0 |
T141 |
68144 |
69 |
0 |
0 |
T142 |
14003 |
17 |
0 |
0 |
T143 |
12506 |
21 |
0 |
0 |
T144 |
10310 |
11 |
0 |
0 |
T145 |
4317 |
10 |
0 |
0 |
T146 |
36433 |
45 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1148 |
0 |
0 |
T112 |
179743 |
462 |
0 |
0 |
T140 |
7974 |
5 |
0 |
0 |
T141 |
68144 |
67 |
0 |
0 |
T142 |
14003 |
1 |
0 |
0 |
T143 |
12506 |
13 |
0 |
0 |
T144 |
10310 |
2 |
0 |
0 |
T146 |
36433 |
48 |
0 |
0 |
T147 |
9707 |
5 |
0 |
0 |
T148 |
10370 |
5 |
0 |
0 |
T149 |
7746 |
3 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1384 |
0 |
0 |
T112 |
179743 |
391 |
0 |
0 |
T118 |
10455 |
10 |
0 |
0 |
T140 |
7974 |
12 |
0 |
0 |
T141 |
68144 |
123 |
0 |
0 |
T142 |
14003 |
6 |
0 |
0 |
T143 |
12506 |
10 |
0 |
0 |
T144 |
10310 |
14 |
0 |
0 |
T145 |
4317 |
1 |
0 |
0 |
T146 |
36433 |
85 |
0 |
0 |
T147 |
9707 |
21 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
7326 |
0 |
0 |
T79 |
2844 |
8 |
0 |
0 |
T112 |
179743 |
441 |
0 |
0 |
T118 |
10455 |
150 |
0 |
0 |
T140 |
7974 |
28 |
0 |
0 |
T141 |
68144 |
1386 |
0 |
0 |
T142 |
14003 |
84 |
0 |
0 |
T143 |
12506 |
18 |
0 |
0 |
T144 |
10310 |
16 |
0 |
0 |
T146 |
36433 |
824 |
0 |
0 |
T147 |
9707 |
23 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
6516 |
0 |
0 |
T79 |
2844 |
10 |
0 |
0 |
T112 |
179743 |
465 |
0 |
0 |
T118 |
10455 |
150 |
0 |
0 |
T140 |
7974 |
32 |
0 |
0 |
T141 |
68144 |
1166 |
0 |
0 |
T142 |
14003 |
17 |
0 |
0 |
T143 |
12506 |
20 |
0 |
0 |
T144 |
10310 |
342 |
0 |
0 |
T146 |
36433 |
152 |
0 |
0 |
T147 |
9707 |
137 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
7290 |
0 |
0 |
T79 |
2844 |
5 |
0 |
0 |
T112 |
179743 |
454 |
0 |
0 |
T118 |
10455 |
107 |
0 |
0 |
T140 |
7974 |
36 |
0 |
0 |
T141 |
68144 |
1479 |
0 |
0 |
T142 |
14003 |
135 |
0 |
0 |
T143 |
12506 |
7 |
0 |
0 |
T144 |
10310 |
105 |
0 |
0 |
T145 |
4317 |
6 |
0 |
0 |
T147 |
9707 |
60 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
6928 |
0 |
0 |
T79 |
2844 |
4 |
0 |
0 |
T112 |
179743 |
418 |
0 |
0 |
T140 |
7974 |
21 |
0 |
0 |
T141 |
68144 |
1320 |
0 |
0 |
T142 |
14003 |
103 |
0 |
0 |
T143 |
12506 |
21 |
0 |
0 |
T144 |
10310 |
107 |
0 |
0 |
T145 |
4317 |
115 |
0 |
0 |
T146 |
36433 |
355 |
0 |
0 |
T147 |
9707 |
76 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
6764 |
0 |
0 |
T79 |
2844 |
12 |
0 |
0 |
T112 |
179743 |
406 |
0 |
0 |
T118 |
10455 |
169 |
0 |
0 |
T140 |
7974 |
25 |
0 |
0 |
T141 |
68144 |
995 |
0 |
0 |
T142 |
14003 |
83 |
0 |
0 |
T143 |
12506 |
30 |
0 |
0 |
T144 |
10310 |
242 |
0 |
0 |
T145 |
4317 |
130 |
0 |
0 |
T147 |
9707 |
64 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
7241 |
0 |
0 |
T79 |
2844 |
7 |
0 |
0 |
T112 |
179743 |
422 |
0 |
0 |
T118 |
10455 |
73 |
0 |
0 |
T140 |
7974 |
29 |
0 |
0 |
T141 |
68144 |
1345 |
0 |
0 |
T142 |
14003 |
185 |
0 |
0 |
T143 |
12506 |
15 |
0 |
0 |
T144 |
10310 |
283 |
0 |
0 |
T145 |
4317 |
2 |
0 |
0 |
T147 |
9707 |
2 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
8192 |
0 |
0 |
T79 |
2844 |
5 |
0 |
0 |
T112 |
179743 |
494 |
0 |
0 |
T118 |
10455 |
132 |
0 |
0 |
T140 |
7974 |
26 |
0 |
0 |
T141 |
68144 |
1376 |
0 |
0 |
T142 |
14003 |
108 |
0 |
0 |
T143 |
12506 |
8 |
0 |
0 |
T144 |
10310 |
143 |
0 |
0 |
T145 |
4317 |
95 |
0 |
0 |
T147 |
9707 |
121 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
7692 |
0 |
0 |
T79 |
2844 |
2 |
0 |
0 |
T112 |
179743 |
433 |
0 |
0 |
T118 |
10455 |
3 |
0 |
0 |
T140 |
7974 |
36 |
0 |
0 |
T141 |
68144 |
1284 |
0 |
0 |
T142 |
14003 |
79 |
0 |
0 |
T143 |
12506 |
39 |
0 |
0 |
T144 |
10310 |
333 |
0 |
0 |
T145 |
4317 |
109 |
0 |
0 |
T147 |
9707 |
42 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3738 |
0 |
0 |
T112 |
179743 |
532 |
0 |
0 |
T118 |
10455 |
49 |
0 |
0 |
T140 |
7974 |
40 |
0 |
0 |
T141 |
68144 |
605 |
0 |
0 |
T142 |
14003 |
57 |
0 |
0 |
T143 |
12506 |
34 |
0 |
0 |
T144 |
10310 |
19 |
0 |
0 |
T145 |
4317 |
56 |
0 |
0 |
T146 |
36433 |
182 |
0 |
0 |
T147 |
9707 |
32 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3204 |
0 |
0 |
T79 |
2844 |
6 |
0 |
0 |
T112 |
179743 |
417 |
0 |
0 |
T118 |
10455 |
2 |
0 |
0 |
T140 |
7974 |
34 |
0 |
0 |
T141 |
68144 |
364 |
0 |
0 |
T142 |
14003 |
16 |
0 |
0 |
T143 |
12506 |
22 |
0 |
0 |
T144 |
10310 |
4 |
0 |
0 |
T145 |
4317 |
58 |
0 |
0 |
T147 |
9707 |
64 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3512 |
0 |
0 |
T79 |
2844 |
6 |
0 |
0 |
T112 |
179743 |
461 |
0 |
0 |
T118 |
10455 |
73 |
0 |
0 |
T140 |
7974 |
10 |
0 |
0 |
T141 |
68144 |
518 |
0 |
0 |
T142 |
14003 |
36 |
0 |
0 |
T143 |
12506 |
21 |
0 |
0 |
T144 |
10310 |
82 |
0 |
0 |
T145 |
4317 |
2 |
0 |
0 |
T147 |
9707 |
37 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3862 |
0 |
0 |
T112 |
179743 |
443 |
0 |
0 |
T118 |
10455 |
39 |
0 |
0 |
T140 |
7974 |
19 |
0 |
0 |
T141 |
68144 |
604 |
0 |
0 |
T142 |
14003 |
40 |
0 |
0 |
T143 |
12506 |
29 |
0 |
0 |
T144 |
10310 |
96 |
0 |
0 |
T145 |
4317 |
55 |
0 |
0 |
T146 |
36433 |
252 |
0 |
0 |
T147 |
9707 |
32 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3743 |
0 |
0 |
T79 |
2844 |
2 |
0 |
0 |
T112 |
179743 |
423 |
0 |
0 |
T118 |
10455 |
43 |
0 |
0 |
T140 |
7974 |
51 |
0 |
0 |
T141 |
68144 |
570 |
0 |
0 |
T142 |
14003 |
8 |
0 |
0 |
T143 |
12506 |
40 |
0 |
0 |
T144 |
10310 |
77 |
0 |
0 |
T146 |
36433 |
285 |
0 |
0 |
T147 |
9707 |
5 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3939 |
0 |
0 |
T79 |
2844 |
5 |
0 |
0 |
T112 |
179743 |
451 |
0 |
0 |
T118 |
10455 |
16 |
0 |
0 |
T140 |
7974 |
34 |
0 |
0 |
T141 |
68144 |
802 |
0 |
0 |
T142 |
14003 |
25 |
0 |
0 |
T143 |
12506 |
28 |
0 |
0 |
T144 |
10310 |
6 |
0 |
0 |
T145 |
4317 |
35 |
0 |
0 |
T147 |
9707 |
43 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3615 |
0 |
0 |
T79 |
2844 |
4 |
0 |
0 |
T112 |
179743 |
450 |
0 |
0 |
T118 |
10455 |
35 |
0 |
0 |
T140 |
7974 |
44 |
0 |
0 |
T141 |
68144 |
465 |
0 |
0 |
T142 |
14003 |
24 |
0 |
0 |
T143 |
12506 |
19 |
0 |
0 |
T144 |
10310 |
60 |
0 |
0 |
T146 |
36433 |
399 |
0 |
0 |
T147 |
9707 |
29 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3918 |
0 |
0 |
T79 |
2844 |
1 |
0 |
0 |
T112 |
179743 |
472 |
0 |
0 |
T118 |
10455 |
33 |
0 |
0 |
T140 |
7974 |
45 |
0 |
0 |
T141 |
68144 |
495 |
0 |
0 |
T142 |
14003 |
20 |
0 |
0 |
T143 |
12506 |
42 |
0 |
0 |
T144 |
10310 |
99 |
0 |
0 |
T145 |
4317 |
33 |
0 |
0 |
T147 |
9707 |
5 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3924 |
0 |
0 |
T112 |
179743 |
466 |
0 |
0 |
T118 |
10455 |
42 |
0 |
0 |
T140 |
7974 |
16 |
0 |
0 |
T141 |
68144 |
683 |
0 |
0 |
T142 |
14003 |
55 |
0 |
0 |
T143 |
12506 |
40 |
0 |
0 |
T144 |
10310 |
105 |
0 |
0 |
T146 |
36433 |
294 |
0 |
0 |
T147 |
9707 |
17 |
0 |
0 |
T148 |
10370 |
62 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3763 |
0 |
0 |
T79 |
2844 |
4 |
0 |
0 |
T112 |
179743 |
475 |
0 |
0 |
T118 |
10455 |
35 |
0 |
0 |
T140 |
7974 |
67 |
0 |
0 |
T141 |
68144 |
608 |
0 |
0 |
T142 |
14003 |
68 |
0 |
0 |
T143 |
12506 |
30 |
0 |
0 |
T144 |
10310 |
112 |
0 |
0 |
T146 |
36433 |
272 |
0 |
0 |
T147 |
9707 |
7 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3717 |
0 |
0 |
T79 |
2844 |
9 |
0 |
0 |
T112 |
179743 |
452 |
0 |
0 |
T118 |
10455 |
10 |
0 |
0 |
T140 |
7974 |
7 |
0 |
0 |
T141 |
68144 |
572 |
0 |
0 |
T142 |
14003 |
20 |
0 |
0 |
T143 |
12506 |
26 |
0 |
0 |
T144 |
10310 |
124 |
0 |
0 |
T145 |
4317 |
3 |
0 |
0 |
T147 |
9707 |
37 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3592 |
0 |
0 |
T112 |
179743 |
417 |
0 |
0 |
T118 |
10455 |
25 |
0 |
0 |
T140 |
7974 |
40 |
0 |
0 |
T141 |
68144 |
477 |
0 |
0 |
T142 |
14003 |
37 |
0 |
0 |
T143 |
12506 |
5 |
0 |
0 |
T144 |
10310 |
135 |
0 |
0 |
T145 |
4317 |
64 |
0 |
0 |
T146 |
36433 |
335 |
0 |
0 |
T147 |
9707 |
34 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3818 |
0 |
0 |
T79 |
2844 |
3 |
0 |
0 |
T112 |
179743 |
477 |
0 |
0 |
T118 |
10455 |
65 |
0 |
0 |
T141 |
68144 |
689 |
0 |
0 |
T142 |
14003 |
27 |
0 |
0 |
T143 |
12506 |
35 |
0 |
0 |
T144 |
10310 |
48 |
0 |
0 |
T145 |
4317 |
49 |
0 |
0 |
T146 |
36433 |
239 |
0 |
0 |
T147 |
9707 |
64 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3795 |
0 |
0 |
T79 |
2844 |
5 |
0 |
0 |
T112 |
179743 |
464 |
0 |
0 |
T118 |
10455 |
27 |
0 |
0 |
T140 |
7974 |
38 |
0 |
0 |
T141 |
68144 |
484 |
0 |
0 |
T142 |
14003 |
67 |
0 |
0 |
T143 |
12506 |
14 |
0 |
0 |
T144 |
10310 |
103 |
0 |
0 |
T145 |
4317 |
46 |
0 |
0 |
T147 |
9707 |
61 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3861 |
0 |
0 |
T112 |
179743 |
416 |
0 |
0 |
T118 |
10455 |
48 |
0 |
0 |
T140 |
7974 |
21 |
0 |
0 |
T141 |
68144 |
667 |
0 |
0 |
T142 |
14003 |
27 |
0 |
0 |
T143 |
12506 |
21 |
0 |
0 |
T144 |
10310 |
66 |
0 |
0 |
T145 |
4317 |
47 |
0 |
0 |
T146 |
36433 |
214 |
0 |
0 |
T147 |
9707 |
21 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3664 |
0 |
0 |
T79 |
2844 |
5 |
0 |
0 |
T112 |
179743 |
463 |
0 |
0 |
T118 |
10455 |
34 |
0 |
0 |
T140 |
7974 |
39 |
0 |
0 |
T141 |
68144 |
631 |
0 |
0 |
T142 |
14003 |
67 |
0 |
0 |
T143 |
12506 |
53 |
0 |
0 |
T144 |
10310 |
12 |
0 |
0 |
T145 |
4317 |
37 |
0 |
0 |
T147 |
9707 |
62 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
4075 |
0 |
0 |
T79 |
2844 |
3 |
0 |
0 |
T112 |
179743 |
410 |
0 |
0 |
T118 |
10455 |
6 |
0 |
0 |
T140 |
7974 |
24 |
0 |
0 |
T141 |
68144 |
611 |
0 |
0 |
T142 |
14003 |
52 |
0 |
0 |
T143 |
12506 |
19 |
0 |
0 |
T144 |
10310 |
135 |
0 |
0 |
T145 |
4317 |
48 |
0 |
0 |
T147 |
9707 |
54 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3561 |
0 |
0 |
T79 |
2844 |
4 |
0 |
0 |
T112 |
179743 |
456 |
0 |
0 |
T118 |
10455 |
50 |
0 |
0 |
T140 |
7974 |
14 |
0 |
0 |
T141 |
68144 |
483 |
0 |
0 |
T142 |
14003 |
77 |
0 |
0 |
T143 |
12506 |
14 |
0 |
0 |
T144 |
10310 |
120 |
0 |
0 |
T145 |
4317 |
6 |
0 |
0 |
T147 |
9707 |
32 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3760 |
0 |
0 |
T79 |
2844 |
5 |
0 |
0 |
T112 |
179743 |
461 |
0 |
0 |
T118 |
10455 |
48 |
0 |
0 |
T140 |
7974 |
32 |
0 |
0 |
T141 |
68144 |
625 |
0 |
0 |
T142 |
14003 |
56 |
0 |
0 |
T143 |
12506 |
7 |
0 |
0 |
T144 |
10310 |
35 |
0 |
0 |
T146 |
36433 |
353 |
0 |
0 |
T147 |
9707 |
37 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3272 |
0 |
0 |
T112 |
179743 |
443 |
0 |
0 |
T118 |
10455 |
37 |
0 |
0 |
T140 |
7974 |
19 |
0 |
0 |
T141 |
68144 |
320 |
0 |
0 |
T142 |
14003 |
85 |
0 |
0 |
T143 |
12506 |
40 |
0 |
0 |
T144 |
10310 |
13 |
0 |
0 |
T145 |
4317 |
3 |
0 |
0 |
T146 |
36433 |
261 |
0 |
0 |
T147 |
9707 |
64 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3518 |
0 |
0 |
T79 |
2844 |
9 |
0 |
0 |
T112 |
179743 |
494 |
0 |
0 |
T118 |
10455 |
44 |
0 |
0 |
T140 |
7974 |
35 |
0 |
0 |
T141 |
68144 |
441 |
0 |
0 |
T142 |
14003 |
30 |
0 |
0 |
T143 |
12506 |
14 |
0 |
0 |
T144 |
10310 |
114 |
0 |
0 |
T145 |
4317 |
45 |
0 |
0 |
T147 |
9707 |
31 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3340 |
0 |
0 |
T79 |
2844 |
5 |
0 |
0 |
T112 |
179743 |
472 |
0 |
0 |
T118 |
10455 |
25 |
0 |
0 |
T140 |
7974 |
12 |
0 |
0 |
T141 |
68144 |
497 |
0 |
0 |
T142 |
14003 |
45 |
0 |
0 |
T143 |
12506 |
5 |
0 |
0 |
T144 |
10310 |
11 |
0 |
0 |
T145 |
4317 |
38 |
0 |
0 |
T147 |
9707 |
47 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3889 |
0 |
0 |
T79 |
2844 |
5 |
0 |
0 |
T112 |
179743 |
449 |
0 |
0 |
T118 |
10455 |
87 |
0 |
0 |
T141 |
68144 |
616 |
0 |
0 |
T142 |
14003 |
27 |
0 |
0 |
T143 |
12506 |
12 |
0 |
0 |
T144 |
10310 |
167 |
0 |
0 |
T145 |
4317 |
6 |
0 |
0 |
T146 |
36433 |
338 |
0 |
0 |
T147 |
9707 |
36 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3937 |
0 |
0 |
T79 |
2844 |
11 |
0 |
0 |
T112 |
179743 |
463 |
0 |
0 |
T118 |
10455 |
61 |
0 |
0 |
T140 |
7974 |
40 |
0 |
0 |
T141 |
68144 |
657 |
0 |
0 |
T142 |
14003 |
75 |
0 |
0 |
T143 |
12506 |
23 |
0 |
0 |
T144 |
10310 |
102 |
0 |
0 |
T145 |
4317 |
60 |
0 |
0 |
T147 |
9707 |
7 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1406 |
0 |
0 |
T112 |
179743 |
455 |
0 |
0 |
T118 |
10455 |
4 |
0 |
0 |
T140 |
7974 |
23 |
0 |
0 |
T141 |
68144 |
132 |
0 |
0 |
T142 |
14003 |
19 |
0 |
0 |
T143 |
12506 |
29 |
0 |
0 |
T144 |
10310 |
19 |
0 |
0 |
T145 |
4317 |
8 |
0 |
0 |
T146 |
36433 |
34 |
0 |
0 |
T147 |
9707 |
17 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1434 |
0 |
0 |
T79 |
2844 |
7 |
0 |
0 |
T112 |
179743 |
462 |
0 |
0 |
T118 |
10455 |
3 |
0 |
0 |
T140 |
7974 |
24 |
0 |
0 |
T141 |
68144 |
140 |
0 |
0 |
T142 |
14003 |
24 |
0 |
0 |
T143 |
12506 |
14 |
0 |
0 |
T144 |
10310 |
12 |
0 |
0 |
T145 |
4317 |
7 |
0 |
0 |
T146 |
36433 |
39 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1356 |
0 |
0 |
T79 |
2844 |
1 |
0 |
0 |
T112 |
179743 |
428 |
0 |
0 |
T118 |
10455 |
21 |
0 |
0 |
T140 |
7974 |
29 |
0 |
0 |
T141 |
68144 |
91 |
0 |
0 |
T142 |
14003 |
22 |
0 |
0 |
T144 |
10310 |
18 |
0 |
0 |
T146 |
36433 |
50 |
0 |
0 |
T147 |
9707 |
8 |
0 |
0 |
T149 |
7746 |
7 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1490 |
0 |
0 |
T79 |
2844 |
4 |
0 |
0 |
T112 |
179743 |
428 |
0 |
0 |
T118 |
10455 |
8 |
0 |
0 |
T140 |
7974 |
52 |
0 |
0 |
T141 |
68144 |
99 |
0 |
0 |
T142 |
14003 |
39 |
0 |
0 |
T143 |
12506 |
23 |
0 |
0 |
T144 |
10310 |
15 |
0 |
0 |
T145 |
4317 |
7 |
0 |
0 |
T147 |
9707 |
1 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1829 |
0 |
0 |
T79 |
2844 |
2 |
0 |
0 |
T112 |
179743 |
481 |
0 |
0 |
T118 |
10455 |
6 |
0 |
0 |
T140 |
7974 |
47 |
0 |
0 |
T141 |
68144 |
219 |
0 |
0 |
T142 |
14003 |
25 |
0 |
0 |
T143 |
12506 |
15 |
0 |
0 |
T144 |
10310 |
24 |
0 |
0 |
T145 |
4317 |
15 |
0 |
0 |
T147 |
9707 |
24 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
3250 |
0 |
0 |
T7 |
775133 |
3 |
0 |
0 |
T8 |
1608 |
0 |
0 |
0 |
T9 |
33600 |
0 |
0 |
0 |
T10 |
714182 |
0 |
0 |
0 |
T11 |
9525 |
0 |
0 |
0 |
T12 |
1865 |
0 |
0 |
0 |
T13 |
3481 |
0 |
0 |
0 |
T14 |
588531 |
0 |
0 |
0 |
T15 |
94502 |
0 |
0 |
0 |
T22 |
0 |
16 |
0 |
0 |
T23 |
61850 |
0 |
0 |
0 |
T52 |
0 |
24 |
0 |
0 |
T150 |
0 |
19 |
0 |
0 |
T151 |
0 |
21 |
0 |
0 |
T152 |
0 |
30 |
0 |
0 |
T153 |
0 |
9 |
0 |
0 |
T154 |
0 |
22 |
0 |
0 |
T155 |
0 |
53 |
0 |
0 |
T156 |
0 |
11 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1392 |
0 |
0 |
T112 |
179743 |
410 |
0 |
0 |
T118 |
10455 |
8 |
0 |
0 |
T140 |
7974 |
48 |
0 |
0 |
T141 |
68144 |
124 |
0 |
0 |
T142 |
14003 |
16 |
0 |
0 |
T143 |
12506 |
37 |
0 |
0 |
T144 |
10310 |
15 |
0 |
0 |
T145 |
4317 |
8 |
0 |
0 |
T146 |
36433 |
56 |
0 |
0 |
T147 |
9707 |
5 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1481 |
0 |
0 |
T79 |
2844 |
5 |
0 |
0 |
T112 |
179743 |
469 |
0 |
0 |
T118 |
10455 |
6 |
0 |
0 |
T140 |
7974 |
33 |
0 |
0 |
T141 |
68144 |
129 |
0 |
0 |
T142 |
14003 |
18 |
0 |
0 |
T143 |
12506 |
45 |
0 |
0 |
T144 |
10310 |
7 |
0 |
0 |
T145 |
4317 |
2 |
0 |
0 |
T147 |
9707 |
12 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1240 |
0 |
0 |
T112 |
179743 |
394 |
0 |
0 |
T140 |
7974 |
2 |
0 |
0 |
T141 |
68144 |
110 |
0 |
0 |
T142 |
14003 |
25 |
0 |
0 |
T143 |
12506 |
29 |
0 |
0 |
T144 |
10310 |
16 |
0 |
0 |
T145 |
4317 |
9 |
0 |
0 |
T146 |
36433 |
55 |
0 |
0 |
T147 |
9707 |
3 |
0 |
0 |
T148 |
10370 |
4 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1200 |
0 |
0 |
T112 |
179743 |
441 |
0 |
0 |
T118 |
10455 |
5 |
0 |
0 |
T140 |
7974 |
26 |
0 |
0 |
T141 |
68144 |
46 |
0 |
0 |
T142 |
14003 |
11 |
0 |
0 |
T143 |
12506 |
22 |
0 |
0 |
T144 |
10310 |
14 |
0 |
0 |
T145 |
4317 |
7 |
0 |
0 |
T146 |
36433 |
41 |
0 |
0 |
T147 |
9707 |
8 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1158 |
0 |
0 |
T79 |
2844 |
2 |
0 |
0 |
T112 |
179743 |
400 |
0 |
0 |
T118 |
10455 |
5 |
0 |
0 |
T140 |
7974 |
7 |
0 |
0 |
T141 |
68144 |
61 |
0 |
0 |
T142 |
14003 |
17 |
0 |
0 |
T143 |
12506 |
14 |
0 |
0 |
T144 |
10310 |
11 |
0 |
0 |
T145 |
4317 |
3 |
0 |
0 |
T147 |
9707 |
6 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1136 |
0 |
0 |
T79 |
2844 |
2 |
0 |
0 |
T112 |
179743 |
412 |
0 |
0 |
T118 |
10455 |
9 |
0 |
0 |
T141 |
68144 |
99 |
0 |
0 |
T143 |
12506 |
10 |
0 |
0 |
T144 |
10310 |
9 |
0 |
0 |
T145 |
4317 |
3 |
0 |
0 |
T146 |
36433 |
24 |
0 |
0 |
T147 |
9707 |
5 |
0 |
0 |
T148 |
10370 |
14 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1924 |
0 |
0 |
T112 |
179743 |
457 |
0 |
0 |
T118 |
10455 |
12 |
0 |
0 |
T140 |
7974 |
8 |
0 |
0 |
T141 |
68144 |
215 |
0 |
0 |
T142 |
14003 |
20 |
0 |
0 |
T143 |
12506 |
14 |
0 |
0 |
T144 |
10310 |
36 |
0 |
0 |
T145 |
4317 |
4 |
0 |
0 |
T146 |
36433 |
90 |
0 |
0 |
T147 |
9707 |
2 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1298 |
0 |
0 |
T112 |
179743 |
485 |
0 |
0 |
T118 |
10455 |
13 |
0 |
0 |
T140 |
7974 |
18 |
0 |
0 |
T141 |
68144 |
75 |
0 |
0 |
T142 |
14003 |
25 |
0 |
0 |
T143 |
12506 |
12 |
0 |
0 |
T144 |
10310 |
13 |
0 |
0 |
T146 |
36433 |
52 |
0 |
0 |
T147 |
9707 |
18 |
0 |
0 |
T148 |
10370 |
2 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
2118 |
0 |
0 |
T79 |
2844 |
2 |
0 |
0 |
T112 |
179743 |
409 |
0 |
0 |
T118 |
10455 |
6 |
0 |
0 |
T140 |
7974 |
7 |
0 |
0 |
T141 |
68144 |
206 |
0 |
0 |
T142 |
14003 |
30 |
0 |
0 |
T143 |
12506 |
42 |
0 |
0 |
T144 |
10310 |
21 |
0 |
0 |
T145 |
4317 |
6 |
0 |
0 |
T146 |
36433 |
164 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1404 |
0 |
0 |
T79 |
2844 |
4 |
0 |
0 |
T112 |
179743 |
468 |
0 |
0 |
T118 |
10455 |
6 |
0 |
0 |
T140 |
7974 |
46 |
0 |
0 |
T141 |
68144 |
127 |
0 |
0 |
T142 |
14003 |
7 |
0 |
0 |
T143 |
12506 |
12 |
0 |
0 |
T144 |
10310 |
14 |
0 |
0 |
T146 |
36433 |
47 |
0 |
0 |
T147 |
9707 |
21 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1334 |
0 |
0 |
T79 |
2844 |
4 |
0 |
0 |
T112 |
179743 |
537 |
0 |
0 |
T118 |
10455 |
10 |
0 |
0 |
T140 |
7974 |
39 |
0 |
0 |
T141 |
68144 |
78 |
0 |
0 |
T142 |
14003 |
11 |
0 |
0 |
T143 |
12506 |
21 |
0 |
0 |
T144 |
10310 |
3 |
0 |
0 |
T145 |
4317 |
9 |
0 |
0 |
T147 |
9707 |
11 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1266 |
0 |
0 |
T112 |
179743 |
458 |
0 |
0 |
T118 |
10455 |
10 |
0 |
0 |
T140 |
7974 |
4 |
0 |
0 |
T141 |
68144 |
98 |
0 |
0 |
T142 |
14003 |
16 |
0 |
0 |
T143 |
12506 |
22 |
0 |
0 |
T144 |
10310 |
1 |
0 |
0 |
T145 |
4317 |
9 |
0 |
0 |
T146 |
36433 |
37 |
0 |
0 |
T148 |
10370 |
8 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1274 |
0 |
0 |
T79 |
2844 |
3 |
0 |
0 |
T112 |
179743 |
443 |
0 |
0 |
T118 |
10455 |
2 |
0 |
0 |
T140 |
7974 |
66 |
0 |
0 |
T141 |
68144 |
77 |
0 |
0 |
T142 |
14003 |
9 |
0 |
0 |
T143 |
12506 |
10 |
0 |
0 |
T144 |
10310 |
9 |
0 |
0 |
T145 |
4317 |
3 |
0 |
0 |
T147 |
9707 |
9 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1205 |
0 |
0 |
T79 |
2844 |
3 |
0 |
0 |
T112 |
179743 |
450 |
0 |
0 |
T118 |
10455 |
11 |
0 |
0 |
T140 |
7974 |
52 |
0 |
0 |
T141 |
68144 |
68 |
0 |
0 |
T142 |
14003 |
13 |
0 |
0 |
T143 |
12506 |
24 |
0 |
0 |
T144 |
10310 |
8 |
0 |
0 |
T145 |
4317 |
6 |
0 |
0 |
T147 |
9707 |
22 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1274 |
0 |
0 |
T79 |
2844 |
9 |
0 |
0 |
T112 |
179743 |
457 |
0 |
0 |
T118 |
10455 |
10 |
0 |
0 |
T140 |
7974 |
26 |
0 |
0 |
T141 |
68144 |
88 |
0 |
0 |
T142 |
14003 |
5 |
0 |
0 |
T143 |
12506 |
25 |
0 |
0 |
T144 |
10310 |
6 |
0 |
0 |
T145 |
4317 |
6 |
0 |
0 |
T147 |
9707 |
6 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449804800 |
1143 |
0 |
0 |
T79 |
2844 |
5 |
0 |
0 |
T112 |
179743 |
423 |
0 |
0 |
T118 |
10455 |
8 |
0 |
0 |
T140 |
7974 |
17 |
0 |
0 |
T141 |
68144 |
58 |
0 |
0 |
T142 |
14003 |
14 |
0 |
0 |
T143 |
12506 |
12 |
0 |
0 |
T144 |
10310 |
7 |
0 |
0 |
T146 |
36433 |
31 |
0 |
0 |
T147 |
9707 |
13 |
0 |
0 |