Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3565154	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4491176

1

T1

4748

T2

4

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4320245	1			T1	480		T2	1		T3	1
values[0x0]	1867079	1			T1	2265		T2	13		T4	18
values[0x1]	1869006	1			T1	2140		T2	7		T4	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2533589	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5522741

1

T1

4781

T2

4

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	37954	1			T1	9		T5	1		T6	76
valid_sources[0x01]	31432	1			T1	29		T5	12		T6	81
valid_sources[0x02]	36658	1			T1	15		T5	2		T6	145
valid_sources[0x03]	29317	1			T1	6		T5	6		T6	138
valid_sources[0x04]	28830	1			T1	13		T5	5		T6	52
valid_sources[0x05]	30918	1			T1	21		T5	10		T6	217
valid_sources[0x06]	27133	1			T1	20		T5	3		T6	84
valid_sources[0x07]	32040	1			T1	18		T4	1		T5	3
valid_sources[0x08]	34612	1			T1	24		T5	10		T6	17
valid_sources[0x09]	29931	1			T1	34		T5	6		T6	173
valid_sources[0x0a]	25820	1			T1	13		T4	1		T5	4
valid_sources[0x0b]	29736	1			T1	23		T5	3		T6	122
valid_sources[0x0c]	33313	1			T1	14		T5	3		T6	75
valid_sources[0x0d]	34229	1			T1	19		T5	3		T6	84
valid_sources[0x0e]	29441	1			T1	16		T5	2		T6	85
valid_sources[0x0f]	40694	1			T1	10		T5	5		T6	98
valid_sources[0x10]	30206	1			T1	20		T5	6		T6	86
valid_sources[0x11]	32526	1			T1	23		T5	9		T6	73
valid_sources[0x12]	31200	1			T1	25		T5	5		T6	80
valid_sources[0x13]	30783	1			T1	9		T4	2		T5	1
valid_sources[0x14]	31455	1			T1	16		T4	1		T5	1
valid_sources[0x15]	29683	1			T1	16		T5	4		T6	26
valid_sources[0x16]	30354	1			T1	14		T5	5		T6	138
valid_sources[0x17]	27638	1			T1	18		T5	11		T6	64
valid_sources[0x18]	31308	1			T1	23		T4	1		T5	8
valid_sources[0x19]	47791	1			T1	9		T4	1		T5	6
valid_sources[0x1a]	27904	1			T1	25		T5	8		T6	192
valid_sources[0x1b]	33178	1			T1	19		T5	1		T6	110
valid_sources[0x1c]	29968	1			T1	21		T6	95		T7	12
valid_sources[0x1d]	29627	1			T1	50		T5	5		T6	86
valid_sources[0x1e]	28320	1			T1	25		T5	5		T6	43
valid_sources[0x1f]	27693	1			T1	12		T5	4		T6	61
valid_sources[0x20]	29993	1			T1	8		T5	17		T6	78
valid_sources[0x21]	27660	1			T1	23		T5	6		T6	90
valid_sources[0x22]	29883	1			T1	12		T5	4		T6	80
valid_sources[0x23]	34281	1			T1	31		T4	1		T5	2
valid_sources[0x24]	28212	1			T1	15		T5	5		T6	55
valid_sources[0x25]	29835	1			T1	14		T5	8		T6	59
valid_sources[0x26]	28970	1			T1	16		T5	5		T6	53
valid_sources[0x27]	40822	1			T1	14		T5	7		T6	69
valid_sources[0x28]	31227	1			T1	25		T5	3		T6	76
valid_sources[0x29]	31160	1			T1	12		T4	1		T5	2
valid_sources[0x2a]	28665	1			T1	34		T5	6		T6	134
valid_sources[0x2b]	27336	1			T1	23		T5	2		T6	83
valid_sources[0x2c]	31691	1			T1	14		T5	7		T6	42
valid_sources[0x2d]	35090	1			T1	7		T5	9		T6	82
valid_sources[0x2e]	34411	1			T1	14		T5	3		T6	97
valid_sources[0x2f]	32606	1			T1	21		T5	7		T6	53
valid_sources[0x30]	28618	1			T1	19		T5	2		T6	150
valid_sources[0x31]	32963	1			T1	8		T5	8		T6	166
valid_sources[0x32]	33011	1			T1	17		T5	6		T6	31
valid_sources[0x33]	27681	1			T1	17		T2	13		T6	99
valid_sources[0x34]	29992	1			T1	24		T5	3		T6	105
valid_sources[0x35]	29042	1			T1	19		T5	8		T6	111
valid_sources[0x36]	28825	1			T1	21		T5	7		T6	70
valid_sources[0x37]	30278	1			T1	15		T5	4		T6	110
valid_sources[0x38]	31641	1			T1	14		T5	4		T6	81
valid_sources[0x39]	31955	1			T1	32		T5	3		T6	208
valid_sources[0x3a]	29589	1			T1	25		T5	7		T6	126
valid_sources[0x3b]	28661	1			T1	21		T5	2		T6	107
valid_sources[0x3c]	33145	1			T1	39		T5	2		T6	93
valid_sources[0x3d]	28272	1			T1	14		T5	7		T6	27
valid_sources[0x3e]	28733	1			T1	15		T5	2		T6	164
valid_sources[0x3f]	31071	1			T1	14		T5	3		T6	69
valid_sources[0x40]	31204	1			T1	17		T5	3		T6	135
valid_sources[0x41]	27734	1			T1	21		T4	1		T5	5
valid_sources[0x42]	30526	1			T1	23		T5	2		T6	67
valid_sources[0x43]	30020	1			T1	28		T5	6		T6	119
valid_sources[0x44]	31685	1			T1	32		T5	4		T6	150
valid_sources[0x45]	31598	1			T1	38		T5	9		T6	111
valid_sources[0x46]	30257	1			T1	27		T5	4		T6	58
valid_sources[0x47]	27913	1			T1	9		T5	9		T6	107
valid_sources[0x48]	32098	1			T1	11		T5	5		T6	57
valid_sources[0x49]	31887	1			T1	28		T5	3		T6	150
valid_sources[0x4a]	30140	1			T1	61		T5	2		T6	118
valid_sources[0x4b]	30232	1			T1	23		T5	1		T6	249
valid_sources[0x4c]	28904	1			T1	10		T5	3		T6	264
valid_sources[0x4d]	29293	1			T1	8		T5	1		T6	122
valid_sources[0x4e]	30913	1			T1	25		T5	5		T6	91
valid_sources[0x4f]	31190	1			T1	18		T5	3		T6	104
valid_sources[0x50]	28250	1			T1	29		T5	5		T6	202
valid_sources[0x51]	31828	1			T1	17		T6	125		T7	8
valid_sources[0x52]	35571	1			T1	31		T5	1		T6	117
valid_sources[0x53]	27494	1			T1	20		T5	1		T6	61
valid_sources[0x54]	30005	1			T1	17		T4	1		T5	4
valid_sources[0x55]	32125	1			T1	24		T5	6		T6	75
valid_sources[0x56]	31031	1			T1	18		T5	3		T6	98
valid_sources[0x57]	30744	1			T1	22		T5	2		T6	143
valid_sources[0x58]	28893	1			T1	20		T5	2		T6	95
valid_sources[0x59]	29123	1			T1	21		T5	3		T6	149
valid_sources[0x5a]	30237	1			T1	19		T5	9		T6	140
valid_sources[0x5b]	30834	1			T1	24		T4	1		T5	3
valid_sources[0x5c]	33818	1			T1	11		T5	8		T6	168
valid_sources[0x5d]	30062	1			T1	17		T5	3		T6	157
valid_sources[0x5e]	28780	1			T1	16		T5	9		T6	81
valid_sources[0x5f]	29490	1			T1	29		T5	6		T6	97
valid_sources[0x60]	28763	1			T1	9		T5	4		T6	110
valid_sources[0x61]	32888	1			T1	43		T4	1		T5	7
valid_sources[0x62]	40654	1			T1	12		T5	2		T6	83
valid_sources[0x63]	30284	1			T1	16		T5	2		T6	58
valid_sources[0x64]	31967	1			T1	20		T5	5		T6	73
valid_sources[0x65]	29108	1			T1	26		T5	6		T6	154
valid_sources[0x66]	27030	1			T1	26		T5	3		T6	82
valid_sources[0x67]	29078	1			T1	15		T5	4		T6	115
valid_sources[0x68]	29636	1			T1	13		T5	9		T6	58
valid_sources[0x69]	33199	1			T1	17		T5	3		T6	60
valid_sources[0x6a]	32559	1			T1	15		T5	1		T6	77
valid_sources[0x6b]	27721	1			T1	8		T5	10		T6	121
valid_sources[0x6c]	28124	1			T1	8		T5	3		T6	43
valid_sources[0x6d]	28275	1			T1	21		T5	4		T6	116
valid_sources[0x6e]	29371	1			T1	22		T4	1		T5	6
valid_sources[0x6f]	28260	1			T1	17		T5	6		T6	178
valid_sources[0x70]	32822	1			T1	18		T5	3		T6	38
valid_sources[0x71]	31507	1			T1	12		T5	4		T6	32
valid_sources[0x72]	32134	1			T1	14		T5	1		T6	42
valid_sources[0x73]	30090	1			T1	9		T5	1		T6	111
valid_sources[0x74]	35288	1			T1	19		T5	3		T6	129
valid_sources[0x75]	32123	1			T1	17		T4	1		T5	3
valid_sources[0x76]	35599	1			T1	18		T5	4		T6	27
valid_sources[0x77]	29878	1			T1	15		T5	1		T6	73
valid_sources[0x78]	41920	1			T1	20		T5	1		T6	85
valid_sources[0x79]	27757	1			T1	20		T5	9		T6	88
valid_sources[0x7a]	27818	1			T1	22		T5	8		T6	33
valid_sources[0x7b]	28120	1			T1	22		T4	1		T5	6
valid_sources[0x7c]	28858	1			T1	31		T5	2		T6	111
valid_sources[0x7d]	27824	1			T1	18		T5	4		T6	92
valid_sources[0x7e]	47882	1			T1	24		T5	3		T6	124
valid_sources[0x7f]	28063	1			T1	16		T5	5		T6	58
valid_sources[0x80]	27971	1			T1	10		T5	4		T6	168

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1091975

1

T1

366

T3

1

T4

1

values[0x0]

all_enables

biggest_size

1711382

1

T1

2255

T2

3

T4

13

values[0x1]

all_enables

biggest_size

1687819

1

T1

2127

T2

1

T4

8