Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3586741

1

T1

137

T2

17

T4

10

full_word

4492431

1

T1

4748

T2

4

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8078802	1			T1	4885		T2	21		T3	1
auto[TlIntgErrCmd]	122	1			T58	6		T82	10		T83	8
auto[TlIntgErrData]	120	1			T58	9		T82	10		T83	8
auto[TlIntgErrBoth]	128	1			T58	5		T82	10		T83	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4324822

1

T1

480

T2

1

T3

1

auto[1]

3754350

1

T1

4405

T2

20

T4

31

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3232327	1			T1	114		T2	1		T5	116
auto[TlIntgErrNone]	partial	auto[1]	354078	1			T1	23		T2	16		T4	10
auto[TlIntgErrNone]	full_word	auto[0]	1092329	1			T1	366		T3	1		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	3400068	1			T1	4382		T2	4		T4	21
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T58	4		T82	5		T83	4
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T58	2		T82	5		T83	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T97	1		T151	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T83	1		T161	1		T158	2
auto[TlIntgErrData]	partial	auto[0]	54	1			T58	5		T82	2		T83	5
auto[TlIntgErrData]	partial	auto[1]	50	1			T58	3		T82	5		T83	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T97	1		T159	1		T162	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T58	1		T82	3		T97	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T58	2		T82	6		T97	1
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T58	3		T82	4		T83	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T83	1		T163	1		T164	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T151	1		T165	1		T166	1